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ADV7179 (Analog Devices) : Total 30 Pages

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Data Sheet
Chip Scale PAL/NTSC Video Encoder with
Advanced Power Management
ADV7174/ADV7179
FEATURES
ITU-R1 BT601/BT656 YCrCb to PAL/NTSC video encoder
High quality 10-bit video DACs
SSAF™ (super sub-alias filter)
Advanced power management features
CGMS (copy generation management system)
WSS (wide screen signaling)
NTSC M, PAL N2, PAL B/D/G/H/I, PAL-M3 , PAL 60
Single 27 MHz clock required (×2 oversampling)
Macrovision 7.1 (ADV7174 only)
80 dB video SNR
32-bit direct digital synthesizer for color subcarrier
Multistandard video output support:
Composite (CVBS)
Component S-video (Y/C)
Video input data port supports:
CCIR-656 4:2:2 8-bit parallel input format
Programmable simultaneous composite and S-video or RGB
(SCART)/YPbPr video outputs
Programmable luma filters low-pass [PAL/NTSC] notch,
extended SSAF, CIF, and QCIF
Programmable chroma filters (low-pass [0.65 MHz, 1.0 MHz,
1.2 MHz, and 2.0 MHz], CIF, and QCIF)
Programmable VBI (vertical blanking interval)
Programmable subcarrier frequency and phase
Programmable LUMA delay
Individual on/off control of each DAC
CCIR and square pixel operation
Integrated subcarrier locking to external video source
Color signal control/burst signal control
Interlaced/noninterlaced operation
Complete on-chip video timing generator
Programmable multimode master/slave operation
Closed captioning support
Teletext insertion port (PAL-WST)
On-board color bar generation
On-board voltage reference
2-wire serial MPU interface (I2C® compatible and fast I2C)
Single-supply 2.8 V and 3.3 V operation
Small 40-lead 6 mm × 6 mm LFCSP package
−40°C to +85°C at 3.3 V
−20°C to +85°C at 2.8 V
Qualified for automotive applications
APPLICATIONS
Portable video applications
Mobile phones
Digital still cameras
VAA
RESET
COLOR
DATA
P7–P0
FUNCTIONAL BLOCK DIAGRAM
TTXREQ TTX
POWER
MANAGEMENT
CONTROL
(SLEEP MODE)
ADV7174/ADV7179
CGMS AND WSS
INSERTION
BLOCK
TELETEXT
INSERTION
BLOCK
YUV TO
RBG
MATRIX
8
4:2:2 TO
4:4:4
INTER-
8
POLATOR
8
Y8
YCrCb
TO
YUV
U8
MATRIX
V8
ADD 9 INTER- 9
SYNC
POLATOR
8
ADD
BURST 8
8
INTER-
POLATOR 8
PROGRAMMABLE
LUMINANCE
FILTER
10
PROGRAMMABLE
CHROMINANCE
FILTER
10
10
U
V
10
10
M
U 10
L
T
I
P
10
10-BIT
DAC
10-BIT
L DAC
10
E
X
10
10-BIT
E DAC
R
DAC A (PIN 29)
DAC B (PIN 28)
DAC C (PIN 24)
HSYNC
FIELD/VSYNC
BLANK
VIDEO TIMING
GENERATOR
I2C MPU PORT
REAL-TIME
CONTROL
CIRCUIT
10 10
SIN/COS
DDS BLOCK
VOLTAGE
REFERENCE
CIRCUIT
VREF
RSET
COMP
CLOCK
SCLOCK SDATA ALSB
SCRESET/RTC
GND
Figure 1.
1 ITU-R and CCIR are used interchangeably in this document (ITU-R has replaced CCIR recommendations).
2 Throughout the document, N is referenced to PAL – Combination – N.
3 ADV7174 only.
The Macrovision anticopy process is licensed for noncommercial home use only, which is its sole intended use in the device. Contact the sales office for the latest
Macrovision version available.
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2002–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com



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ADV7174/ADV7179
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
2.8 V Specifications ...................................................................... 4
2.8 V Timing Specifications ........................................................ 5
3.3 V Specifications ...................................................................... 6
3.3 V Timing Specifications ........................................................ 7
Absolute Maximum Ratings............................................................ 9
ESD Caution.................................................................................. 9
Pin Configuration and Function Descriptions........................... 10
General Description ....................................................................... 11
Data Path Description................................................................ 11
Internal Filter Response............................................................. 11
Typical Performance Characteristics ........................................... 13
Features ............................................................................................ 16
Color Bar Generation ................................................................ 16
Square Pixel Mode...................................................................... 16
Color Signal Control .................................................................. 16
Burst Signal Control................................................................... 16
NTSC Pedestal Control ............................................................. 16
Pixel Timing Description .......................................................... 16
Subcarrier Reset.......................................................................... 16
Real-Time Control ..................................................................... 16
Power-On Reset .......................................................................... 25
SCH Phase Mode........................................................................ 25
MPU Port Description............................................................... 25
Register Accesses ........................................................................ 26
Register Programming ................................................................... 27
Subaddress Register (SR7–SR0)................................................ 27
Register Select (SR5–SR0) ......................................................... 27
Mode Register 1 (MR1) ............................................................. 29
Mode Register 2 (MR2) ............................................................. 30
Mode Register 3 (MR3) ............................................................. 31
Mode Register 4 (MR4) ............................................................. 32
Data Sheet
Timing Mode Register 0 (TR0) ................................................ 33
Timing Mode Register 1 (TR1) ................................................ 34
Subcarrier Frequency Registers 3–0 ........................................ 35
Subcarrier Phase Register.......................................................... 35
Closed Captioning Even Field Data Registers 1–0 ................ 35
Closed Captioning Odd Field Data Registers 1–0 ................. 36
NTSC Pedestal/PAL Teletext Control Registers 3–0 ............. 36
Teletext Request Control Register (TC07) .............................. 37
CGMS_WSS Register 0 (C/W0)............................................... 37
CGMS_WSS Register 1 (C/W1)............................................... 38
CGMS_WSS Register 2 (C/W2)............................................... 38
Appendix 1—Board Design and Layout Considerations.......... 39
Ground Planes ............................................................................ 39
Power Planes ............................................................................... 39
Supply Decoupling ..................................................................... 40
Digital Signal Interconnect ....................................................... 40
Analog Signal Interconnect....................................................... 40
Appendix 2—Closed Captioning ................................................. 41
Appendix 3—Copy Generation Management System
(CGMS)............................................................................................ 42
Function of CGMS Bits ............................................................. 42
Appendix 4—Wide Screen Signaling (WSS) .............................. 43
Function of WSS Bits ................................................................. 43
Appendix 5—Teletext..................................................................... 44
Teletext Insertion........................................................................ 44
Teletext Protocol......................................................................... 44
Appendix 6—Waveforms .............................................................. 45
NTSC Waveforms (with Pedestal) ........................................... 45
NTSC Waveforms (without Pedestal)...................................... 46
PAL Waveforms .......................................................................... 47
Pb Pr Waveforms........................................................................ 48
Appendix 7—Optional Output Filter .......................................... 49
Appendix 8—Recommended Register Values............................ 50
Outline Dimensions ....................................................................... 52
Ordering Guide .......................................................................... 52
Automotive Products ................................................................. 52
Rev. C | Page 2 of 52



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Data Sheet
REVISION HISTORY
1/15—Rev. B to Rev. C
Updated Outline Dimensions........................................................52
Changes to Ordering Guide...........................................................52
4/09—Rev. A to Rev. B
Changes to Power-On Reset Section ............................................25
Changes to Figure 55 ......................................................................40
Changes to Figure 69, Figure 70, and Figure 72..........................47
Changes to Figure 81 Caption .......................................................52
Changes to Ordering Guide...........................................................52
2/04—Changed from Rev. 0 to Rev. A
Added 2.8 V Version.......................................................... Universal
Format Updated.................................................................. Universal
Device Currents Updated on 3.3 V Specification .......... Universal
Added new Table 1 and renumbered Subsequent Tables.............4
Added new Table 2 and Renumbered Subsequent Tables ...........5
Change to Figure 54 ........................................................................38
Change to Figure 55 ........................................................................39
Change to Figure 79 ........................................................................48
Changed Ordering Guide Temperature Specifications ..............52
Updated Outline Dimensions........................................................52
10/02—Revision 0: Initial Version
ADV7174/ADV7179
Rev. C | Page 3 of 52



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ADV7174/ADV7179
Data Sheet
SPECIFICATIONS
2.8 V SPECIFICATIONS
VAA = 2.8 V, VREF = 1.235 V, RSET = 150 Ω. All specifications TMIN to TMAX1, unless otherwise noted.
Table 1.
Parameter
STATIC PERFORMANCE2
Resolution (Each DAC)
Accuracy (Each DAC)
Integral Nonlinearity
Differential Nonlinearity
DIGITAL INPUTS2
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN
DIGITAL OUTPUTS2
Output High Voltage, VOH
Output Low Voltage, VOL
Three-State Leakage Current
Three-State Output Capacitance
ANALOG OUTPUTS2
Output Current 3
DAC-to-DAC Matching
Output Compliance, VOC
Output Impedance, ROUT
Output Capacitance, COUT
POWER REQUIREMENTS2, 4
VAA
Normal Power Mode
IDAC (Max)5
ICCT6
Low Power Mode
IDAC (Max)5
ICCT6
Sleep Mode
IDAC7
ICCT8
Power Supply Rejection Ratio
Conditions1
RSET = 300 Ω
Guaranteed monotonic
VIN = 0.4 V or 2.4 V
ISOURCE = 400 µA
ISINK = 3.2 mA
RSET = 150 Ω, RL = 37.5 Ω
IOUT = 0 mA
RSET = 150 Ω, RL = 37.5 Ω
COMP = 0.1 µF
Min Typ
Max Unit
10 Bits
±3.0
±1
LSB
LSB
1.6
10
V
0.7 V
±1 µA
pF
2.4
10
V
0.4 V
10 µA
pF
33 34.7 37
mA
2.0 %
0 1.4 V
30 kΩ
30 pF
2.8 V
115 120 mA
30 mA
62 mA
30 mA
0.1
0.001
0.01
0.5
µA
µA
%/%
1 Temperature range TMIN to TMAX: –20°C to +85°C.
2 Guaranteed by characterization.
3 DACs can output 35 mA typically at 2.8 V (RSET = 150 Ω and RL = 37.5 Ω). Full drive into 37.5 Ω load.
4 Power measurements are taken with clock frequency = 27 MHz. Max TJ = 110°C.
5 IDAC is the total current (min corresponds to 5 mA output per DAC, max corresponds to 37 mA output per DAC) to drive all three DACs. Turning off individual DACs
reduces IDAC correspondingly.
6 ICCT (circuit current) is the continuous current required to drive the device.
7 Total DAC current in sleep mode.
8 Total continuous current during sleep mode.
Rev. C | Page 4 of 52






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