DatasheetBay.com



SST402 (Micross) : Total 1 Pages

No Preview Available !

[ Download PDF for PC ]

SST402
LOW NOISE, LOW DRIFT
MONOLITHIC DUAL
N-CHANNEL JFET
Linear Systems replaces discontinued Siliconix SST402
The SST402 is a Low Noise, Low Drift, Monolithic Dual N-Channel JFET
The SST402 is a high-performance monolithic dual
JFET featuring extremely low noise, tight offset voltage
and low drift over temperature specifications, and is
targeted for use in a wide range of precision
instrumentation applications. The SST402 features a 5-
mV offset and 10-µV/°C drift. The SST402 is a direct
replacement for discontinued Siliconix SST402.
FEATURES 
LOW DRIFT 
LOW NOISE 
LOW PINCHOFF 
ABSOLUTE MAXIMUM RATINGS  
@ 25°C (unless otherwise noted) 
| V GS12 / T| = 10µV/°C TYP. 
en = 6nV/Hz @ 10Hz TYP. 
Vp = 2.5V TYP. 
The 8 Pin P-DIP and 8 Pin SOIC provide ease of
manufacturing, and the symmetrical pinout prevents
improper orientation.
Maximum Temperatures 
Storage Temperature 
65°C to +150°C 
Operating Junction Temperature 
+150°C 
Maximum Voltage and Current for Each Transistor  Note 1 
(See Packaging Information).
SST402 Applications:
VGSS 
Gate Voltage to Drain or Source 
VDSO 
Drain to Source Voltage 
IG(f)  Gate Forward Current 
Maximum Power Dissipation 
50V 
50V 
10mA 
Device Dissipation @ Free Air  Total                 300mW 
ƒ Wideband Differential Amps
ƒ High-Speed,Temp-Compensated Single-Ended
Input Amps
ƒ High-Speed Comparators
ƒ Impedance Converters and vibrations detectors.
 
MATCHING CHARACTERISTICS @ 25°C UNLESS OTHERWISE NOTED
SYMBOL 
CHARACTERISTICS  VALUE  UNITS  CONDITIONS 
| V GS12 / T| max. 
DRIFT VS. 
TEMPERATURE 
10  µV/°C  VDG=10V, ID=200µA 
TA=55°C to +125°C 
| V GS12 | max. 
OFFSET VOLTAGE  10 
mV  VDG=10V, ID=200µA 
ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted)
SYMBOL 
CHARACTERISTICS 
MIN. 
TYP.  MAX. 
UNITS 
CONDITIONS 
BVGSS 
BVGGO 
 
YfSS 
ClickYfS 
Breakdown Voltage 
GateToGate Breakdown 
TRANSCONDUCTANCE 
Full Conduction 
Typical Operation 
50 
±50 
 
2000 
1000 
|YFS12 / Y FS| 
Mismatch 
‐‐ 
To Buy60  ‐‐ 
‐‐  ‐‐ 
  
‐‐  7000 
‐‐  2000 
V 
V 
 
µmho 
µmho 
VDS = 0                  ID=1nA 
      I G= 1nA               ID= 0               IS= 0 
 
VDG= 10V         VGS= 0V      f = 1kHz 
     VDG= 15V         ID= 200µA    f = 1kHz 
0.6  3 
% 
 
 
DRAIN CURRENT 
    
 
 
IDSS 
Full Conduction 
0.5  ‐‐  10 
mA 
VDG= 10V              VGS= 0V 
|IDSS12 / IDSS|  Mismatch at Full Conduction 
  GATE VOLTAGE 
‐‐ 
 
1  5 
  
% 
 
 
 
VGS(off) or Vp 
VGS(on) 
 
Pinchoff voltage 
Operating Range 
GATE CURRENT 
0.5  ‐‐  ‐2.5 
‐‐  ‐‐  ‐2.3 
    
V  VDS= 15V               ID= 1nA 
V                VDS=15V                 ID=200µA 
  
IGmax. 
Operating 
‐‐  ‐4  ‐15 
pA 
VDG= 15V ID= 200µA 
IGmax. 
High Temperature 
‐‐  ‐‐  ‐10 
nA  TA= +125°C
 
IGSSmax. 
At Full Conduction 
‐‐  ‐‐  100 
pA 
VDS =0 
IGSSmax. 
 
High Temperature 
OUTPUT CONDUCTANCE 
5 
 
5  5 
  
pA 
 
VDG= 15V         TA= +125°C 
 
YOSS  Full Conduction  ‐‐ 
YOS  Operating  ‐‐ 
 
COMMON MODE REJECTION 
 
‐‐  20 
0.2  2 
  
µmho 
µmho 
 
VDG= 10V              VGS= 0V 
VDG=  15V            ID= 500µA 
 
CMR 
20 log | V GS12/ V DS| 
95  ‐‐  ‐‐ 
dB 
VDS = 10 to 20V        ID=30µA 
 
NOISE 
    
  VDS= 15V      VGS= 0V       RG= 10M 
NF 
Figure 
‐‐  ‐‐  0.5 
dB 
f= 100Hz           NBW= 6Hz 
en 
Voltage 
‐‐ 
20  ‐‐ 
nV/Hz 
VDS=15V   ID=200µA   f=10Hz  NBW=1Hz 
 
CAPACITANCE 
    
 
 
CISS 
Input 
‐‐  ‐‐  8 
pF  VDS= 15V      ID= 200µA      f= 1MHz 
CRSS 
Reverse Transfer 
‐‐  ‐‐  1.5 
pF 
 
Note 1 – These ratings are limiting values above which the serviceability of any semiconductor may be impaired
PDIP / SOIC (Top View)
Micross Components Europe
Available Packages:
SST402 in PDIP / SOIC
SST402 available as bare die
Please cowntwactwM.icDroasstafoSr hfulel peatc4kUag.ecaonmd die dimensions
Tel: +44 1603 788967
Email: chipcomponents@micross.com
Web: http://www.micross.com/distribution
Information furnished by Linear Integrated Systems and Micross Components is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or
other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems.





[ Download PDF for PC ]





0  1  2  3  4  5  6  7  8  9  A  B  C  D  E  F  G  H  I  J  K  L  M  N  O  P  Q  R  S  T  U  V  W  X  Y  Z  

This is a individually operated, non profit site. If this site is good enough to show, please introduce this site to others.
* 2015 :: DatasheetBay.com :: DatasheetBay