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N04L63W2A (ON Semiconductor) : Total 10 Pages

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N04L63W2Awww.DataSheet4U.com
4Mb Ultra-Low Power Asynchronous CMOS SRAM
256K × 16 bit
Overview
Features
The N04L63W2A is an integrated memory device
containing a 4 Mbit Static Random Access Memory
organized as 262,144 words by 16 bits. The device
is designed and fabricated using ON
Semiconductor’s advanced CMOS technology to
provide both high-speed performance and ultra-low
power. The device operates with two chip enable
(CE1 and CE2) controls and output enable (OE) to
allow for easy memory expansion. Byte controls
(UB and LB) allow the upper and lower bytes to be
accessed independently and can also be used to
deselect the device. The N04L63W2A is optimal
for various applications where low-power is critical
such as battery backup and hand-held devices.
The device can operate over a very wide
temperature range of -40oC to +85oC and is
available in JEDEC standard packages compatible
with other standard 256Kb x 16 SRAMs
Product Family
• Single Wide Power Supply Range
2.3 to 3.6 Volts
• Very low standby current
4.0µA at 3.0V (Typical)
• Very low operating current
2.0mA at 3.0V and 1µs (Typical)
• Very low Page Mode operating current
0.8mA at 3.0V and 1µs (Typical)
• Simple memory control
Dual Chip Enables (CE1 and CE2)
Output Enable (OE) for memory expansion
• Low voltage data retention
Vcc = 1.8V
• Very fast output enable access time
25ns OE access time
• Automatic power down to standby mode
• TTL compatible three-state output driver
• Compact space saving BGA package avail-
able
Part Number
N04L63W2AB
N04L63W2AT
N04L63W2AB2
N04L63W2AT2
Package Type
48 - BGA
44 - TSOP II
48 - BGA Green
44 - TSOP II Green
Operating
Temperature
Power
Supply
(Vcc)
Speed
Options
Standby
Operating
Current (ISB), Current (Icc),
Typical
Typical
-40oC to +85oC 2.3V - 3.6V
70ns @ 2.7V
55ns @ 2.7V
4 µA
2 mA @ 1MHz
Pin Configuration
A4
A3
A2
A1
A0
CE1
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
PIN
ONE
44 A5
43 A6
42 A7
41 OE
40 UB
39 LB
38 I/O15
37 I/O14
36 I/O13
35 I/O12
34 VSS
33 VCC
32 I/O11
31 I/O10
30 I/O9
29 I/O8
28 CE2
27 A8
26 A9
25 A10
24 A11
23 A17
123456
A LB OE A0 A1 A2 CE2
B I/O8 UB A3 A4 CE1 I/O0
C I/O9 I/O10 A5 A6 I/O1 I/O2
D VSS I/O11 A17 A7 I/O3 VCC
E VCC I/O12 NC A16 I/O4 VSS
F I/O14 I/O13 A14 A15 I/O5 I/O6
G I/O15 NC A12 A13 WE I/O7
H NC A8 A9 A10 A11 NC
48 Pin BGA (top)
6 x 8 mm
Pin Descriptions
Pin Name
A0-A17
WE
CE1, CE2
OE
LB
UB
I/O0-I/O15
VCC
VSS
NC
Pin Function
Address Inputs
Write Enable Input
Chip Enable Input
Output Enable Input
Lower Byte Enable Input
Upper Byte Enable Input
Data Inputs/Outputs
Power
Ground
Not Connected
©2008 SCILLC. All rights reserved.
July 2008 - Rev. 10
Publication Order Number:
N04L63W2A/D



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N04L63W2A
Functional Block Diagram
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Address
Inputs
A0 - A3
Word
Address
Decode
Logic
Address
Inputs
A4 - A17
Page
Address
Decode
Logic
CE1
CE2
WE
OE
UB
LB
Control
Logic
16K Page
x 16 word
x 16 bit
RAM Array
Input/
Output
Mux
and
Buffers
I/O0 - I/O7
I/O8 - I/O15
Functional Description
CE1 CE2 WE OE UB LB
I/O0 - I/O151
MODE
POWER
HXXXXX
XLXXXX
L HX XHH
L H L X3 L1 L1
L H H L L1 L1
L H H H L1 L1
High Z
High Z
High Z
Data In
Data Out
High Z
Standby2
Standby2
Standby
Write3
Read
Active
Standby
Standby
Standby
Active
Active
Active
1. When UB and LB are in select mode (low), I/O0 - I/O15 are affected as shown. When LB only is in the select mode only I/O0 - I/O7
are affected as shown. When UB is in the select mode only I/O8 - I/O15 are affected as shown.
2. When the device is in standby mode, control inputs (WE, OE, UB, and LB), address inputs and data input/outputs are internally
isolated from any external influence and disabled from exerting any influence externally.
3. When WE is invoked, the OE input is internally disabled and has no effect on the circuit.
Capacitance1
Item
Symbol
Test Condition
Input Capacitance
I/O Capacitance
CIN VIN = 0V, f = 1 MHz, TA = 25oC
CI/O VIN = 0V, f = 1 MHz, TA = 25oC
1. These parameters are verified in device characterization and are not 100% tested
Min Max Unit
8 pF
8 pF
Rev. 10 | Page 2 of 10 | www.onsemi.com



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N04L63W2A
www.DataSheet4U.com
Absolute Maximum Ratings1
Item
Symbol
Rating
Unit
Voltage on any pin relative to VSS
Voltage on VCC Supply Relative to VSS
Power Dissipation
Storage Temperature
Operating Temperature
Soldering Temperature and Time
VIN,OUT
VCC
PD
TSTG
TA
TSOLDER
–0.3 to VCC+0.3
–0.3 to 4.5
500
–40 to 125
-40 to +85
260oC, 10sec
V
V
mW
oC
oC
oC
1. Stresses greater than those listed above may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operating section of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Operating Characteristics (Over Specified Temperature Range)
Item
Symbol
Test Conditions
Min.
Typ1
Max Unit
Supply Voltage
Data Retention Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage Current
Output Leakage Current
Read/Write Operating Supply Current
@ 1 µs Cycle Time2
Read/Write Operating Supply Current
@ 70 ns Cycle Time2
Page Mode Operating Supply Current
@ 70ns Cycle Time2 (Refer to Power
Savings with Page Mode Operation
diagram)
Read/Write Quiescent Operating Sup-
ply Current3
VCC
VDR
VIH
VIL
VOH
VOL
ILI
ILO
ICC1
ICC2
ICC3
ICC4
Maximum Standby Current3
ISB1
Maximum Data Retention Current3
IDR
Chip Disabled3
IOH = 0.2mA
IOL = -0.2mA
VIN = 0 to VCC
OE = VIH or Chip Disabled
VCC=3.6 V, VIN=VIH or VIL
Chip Enabled, IOUT = 0
VCC=3.6 V, VIN=VIH or VIL
Chip Enabled, IOUT = 0
2.3
1.8
1.8
–0.3
VCC–0.2
3.0
2.0
10.0
3.6
3.6
VCC+0.3
0.6
0.2
0.5
0.5
V
V
V
V
V
V
µA
µA
3.0 mA
16.0 mA
VCC=3.6 V, VIN=VIH or VIL
Chip Enabled, IOUT = 0
4.0
mA
VCC=3.6 V, VIN=VIH or VIL
Chip Enabled, IOUT = 0,
f=0
VIN = VCC or 0V
Chip Disabled
tA= 85oC, VCC = 3.6 V
Vcc = 1.8V, VIN = VCC or 0
Chip Disabled, tA= 85oC
2.0 mA
4.0 20.0 µA
10 µA
1. Typical values are measured at Vcc=Vcc Typ., TA=25°C and not 100% tested.
2. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current required to drive
output capacitance expected in the actual system.
3. This device assumes a standby mode if the chip is disabled (CE1 high or CE2 low). In order to achieve low standby current all
inputs must be within 0.2 volts of either VCC or VSS.
Rev. 10 | Page 3 of 10 | www.onsemi.com



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N04L63W2A
Power Savings with Page Mode Operation (WE = VIH)
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Page Address (A4 - A17)
Word Address (A0 - A3)
CE1
CE2
OE
LB, UB
Word 1
Open page
Word 2
...
Word 16
Note: Page mode operation is a method of addressing the SRAM to save operating current. The internal
organization of the SRAM is optimized to allow this unique operating mode to be used as a valuable power
saving feature.
The only thing that needs to be done is to address the SRAM in a manner that the internal page is left open
and 16-bit words of data are read from the open page. By treating addresses A0-A3 as the least significant
bits and addressing the 16 words within the open page, power is reduced to the page mode value which is
considerably lower than standard operating currents for low power SRAMs.
Rev. 10 | Page 4 of 10 | www.onsemi.com






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