DatasheetBay.com



N02L6181A (ON Semiconductor) : Total 11 Pages

No Preview Available !

[ Download PDF for PC ]

N02L6181Awww.DataSheet4U.com
2Mb Ultra-Low Power Asynchronous CMOS SRAM
128Kx16 bit
Features
Overview
The N02L6181A is an integrated memory device
containing a 2 Mbit Static Random Access Memory
organized as 131,072 words by 16 bits. The device
is designed and fabricated using ON
Semiconductor’s advanced CMOS technology to
provide both high-speed performance and ultra-low
power. The base design is the same as ON
Semiconductor’s N02L63W3A, which is processed
to operate at higher voltages. The device operates
with a single chip enable (CE) control and output
enable (OE) to allow for easy memory expansion.
Byte controls (UB and LB) allow the upper and
lower bytes to be accessed independently. The
N02L6181A is optimal for various applications
where low-power is critical such as battery backup
and hand-held devices. The device can operate
over a very wide temperature range of -40oC to
+85oC and is available in JEDEC standard
packages compatible with other standard 128Kb x
16 SRAMs.
Product Family
• Single Wide Power Supply Range
1.65 to 2.2 Volts
• Very low standby current
0.5µA at 1.8V (Typical)
• Very low operating current
1.4mA at 1.8V and 1µs (Typical)
• Very low Page Mode operating current
0.5mA at 1.8V and 1µs (Typical)
• Simple memory control
Single Chip Enable (CE)
Byte control for independent byte operation
Output Enable (OE) for memory expansion
• Low voltage data retention
Vcc = 1.2V
• Very fast output enable access time
30ns OE access time
• Automatic power down to standby mode
• TTL compatible three-state output driver
• Compact space saving BGA package
Part Number
N02L6181AB
N02L6181AB2
Package Type
Operating
Temperature
Power
Supply
(Vcc)
Speed
Standby
Operating
Current (ISB), Current (Icc),
Max Max
48 - BGA
Green 48-BGA
-40oC to +85oC 1.65V - 2.2V
70 and 85ns
@ 1.65V
10 µA
3 mA @ 1MHz
©2008 SCILLC. All rights reserved.
July 2008 - Rev. 4
Publication Order Number:
N02L6181A/D



No Preview Available !

[ Download PDF for PC ]

N02L6181A
Pin Configurations
123456
A LB OE A0 A1 A2 NC
B I/O8 UB A3 A4 CE I/O0
C I/O9 I/O10 A5 A6 I/O1 I/O2
D VSS I/O11 NC A7 I/O3 VCC
E VCC I/O12 NC A16 I/O4 VSS
F I/O14 I/O13 A14 A15 I/O5 I/O6
G I/O15 NC A12 A13 WE I/O7
H NC A8 A9 A10 A11 NC
48 Pin BGA (top)
6 x 8 mm
Pin Descriptions
Pin Name
A0-A16
WE
CE
OE
LB
UB
I/O0-I/O15
NC
VCC
VSS
Pin Function
Address Inputs
Write Enable Input
Chip Enable Input
Output Enable Input
Lower Byte Enable Input
Upper Byte Enable Input
Data Inputs/Outputs
Not Connected
Power
Ground
www.DataSheet4U.com
Rev. 4 | Page 2 of 11 | www.onsemi.com



No Preview Available !

[ Download PDF for PC ]

N02L6181A
Functional Block Diagram
www.DataSheet4U.com
Address
Inputs
A0 - A3
Word
Address
Decode
Logic
Address
Inputs
A4 - A16
Page
Address
Decode
Logic
CE
WE Control
OE Logic
UB
LB
8K Page
x 16 word
x 16 bit
RAM Array
Input/
Output
Mux
and
Buffers
I/O0 - I/O7
I/O8 - I/O15
Functional Description
CE WE OE UB LB
I/O0 - I/O151
MODE
POWER
HXXXX
L XXHH
L L X3 L1 L1
L H L L1 L1
L H H L1 L1
High Z
High Z
Data In
Data Out
High Z
Standby2
Standby2
Write3
Read
Active
Standby
Standby
Active
Active
Active
1. When UB and LB are in select mode (low), I/O0 - I/O15 are affected as shown. When LB only is in the select mode only I/O0 - I/O7
are affected as shown. When UB is in the select mode only I/O8 - I/O15 are affected as shown.
2. When the device is in standby mode, control inputs (WE, OE, UB, and LB), address inputs and data input/outputs are internally
isolated from any external influence and disabled from exerting any influence externally.
3. When WE is invoked, the OE input is internally disabled and has no effect on the circuit.
Capacitance1
Item
Symbol
Test Condition
Input Capacitance
I/O Capacitance
CIN VIN = 0V, f = 1 MHz, TA = 25oC
CI/O VIN = 0V, f = 1 MHz, TA = 25oC
1. These parameters are verified in device characterization and are not 100% tested
Min Max Unit
8 pF
8 pF
Rev. 4 | Page 3 of 11 | www.onsemi.com



No Preview Available !

[ Download PDF for PC ]

N02L6181A
www.DataSheet4U.com
Absolute Maximum Ratings1
Item
Symbol
Rating
Unit
Voltage on any pin relative to VSS
Voltage on VCC Supply Relative to VSS
Power Dissipation
Storage Temperature
Operating Temperature
Soldering Temperature and Time
VIN,OUT
VCC
PD
TSTG
TA
TSOLDER
–0.3 to VCC+0.3
–0.3 to 3.0
500
–40 to 125
-40 to +85
240oC, 10sec(Lead only)
V
V
mW
oC
oC
oC
1. Stresses greater than those listed above may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operating section of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Operating Characteristics (Over Specified Temperature Range)
Item
Symbol
Test Conditions
Min.
Typ1
Max Unit
Supply Voltage
VCC
1.65 1.8
2.2 V
Data Retention Voltage
VDR Chip Disabled2
1.2
2.2 V
Input High Voltage
VIH
0.7Vcc
VCC+0.3 V
Input Low Voltage
VIL
–0.3 0.3Vcc V
Output High Voltage
VOH
IOH = 0.2mA
VCC–0.2
V
Output Low Voltage
VOL IOL = -0.2mA
0.3 V
Input Leakage Current ILI VIN = 0 to VCC
0.5 µA
Output Leakage Current
ILO OE = VIH or Chip Disabled
0.5 µA
Read/Write Operating Supply Current
@ 1 µs Cycle Time2
ICC1
VCC=2.2 V, VIN=VIH or VIL
Chip Enabled, IOUT = 0
1.4 3.0 mA
Read/Write Operating Supply Current
@ 70 ns Cycle Time2
ICC2
VCC=2.2 V, VIN=VIH or VIL
Chip Enabled, IOUT = 0
8.0 17.0 mA
Page Mode Operating Supply Current
@ 70ns Cycle Time2 (Refer to Power
Savings with Page Mode Operation
diagram)
ICC3
VCC=2.2V, VIN=VIH or VIL
Chip Enabled, IOUT = 0
2.0 4.0 mA
Read/Write Quiescent Operating Sup-
ply Current3
ICC4
VCC=2.2V, VIN=VIH or VIL
Chip Enabled, IOUT = 0,
f=0
0.1 mA
Maximum Standby Current3
VIN = VCC or 0V
ISB1 Chip Disabled
tA= 85oC, VCC = 2.2 V
0.5 10.0 µA
Maximum Data Retention Current3
IDR
VCC = 1.2V, VIN = VCC or 0
Chip Disabled, tA= 85oC
5.0 µA
1. Typical values are measured at Vcc=Vcc Typ., TA=25°C and are not 100% tested.
2. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current required to drive
output capacitance expected in the actual system.
3. This device assumes a standby mode if the chip is disabled (CE high). In order to achieve low standby current all inputs must be
within 0.2 volts of either VCC or VSS
Rev. 4 | Page 4 of 11 | www.onsemi.com






[ Download PDF for PC ]






0  1  2  3  4  5  6  7  8  9  A  B  C  D  E  F  G  H  I  J  K  L  M  N  O  P  Q  R  S  T  U  V  W  X  Y  Z  

This is a individually operated, non profit site. If this site is good enough to show, please introduce this site to others.
* 2015 :: DatasheetBay.com :: DatasheetBay