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N01L1618N1A (NanoAmp Solutions) : Total 10 Pages

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NanoAmp Solutions, Inc.
670 North McCarthy Blvd. Suite 220, Milpitas, CA 95035
ph: 408-935-7777, FAX: 408-935-7770
www.nanoamp.com
N01L1618N1Awww.DataSheet4U.com
1Mb Ultra-Low Power Asynchronous CMOS SRAM
64K × 16 bit
Overview
The N01L1618N1A is an integrated memory
device containing a 1 Mbit Static Random Access
Memory organized as 65,536 words by 16 bits. The
device is designed and fabricated using
NanoAmp’s advanced CMOS technology to
provide both high-speed performance and ultra-low
power. The device operates with a single chip
enable (CE) control and output enable (OE) to
allow for easy memory expansion. Byte controls
(UB and LB) allow the upper and lower bytes to be
accessed independently. The N01L1618N1A is
optimal for various applications where low-power is
critical such as battery backup and hand-held
devices. The device can operate over a very wide
temperature range of -40oC to +85oC and is
available in JEDEC standard packages compatible
with other standard 64Kb x 16 SRAMs.
Product Family
Features
• Single Wide Power Supply Range
1.65 to 2.2 Volts
• Very low standby current
0.5µA at 1.8V (Typical)
• Very low operating current
0.7mA at 1.8V and 1µs (Typical)
• Very low Page Mode operating current
0.5mA at 1.8V and 1µs (Typical)
• Simple memory control
Single Chip Enable (CE)
Byte control for independent byte operation
Output Enable (OE) for memory expansion
• Low voltage data retention
Vcc = 1.2V
• Very fast output enable access time
30ns OE access time
• Automatic power down to standby mode
• TTL compatible three-state output driver
• Compact space saving BGA package avail-
able
Part Number
Package Type
Operating
Power
Temperature Supply (Vcc)
Speed
Standby
Operating
Current (ISB), Current (Icc),
Typical
Typical
N01L1618N1AB
48 - BGA
N01L1618N1AT
N01L1618N1AB2
44 - TSOP II
48 - BGA Green
-40oC to +85oC
1.65V - 2.2V
70ns @ 1.8V
85ns @ 1.65V
0.5 µA
0.7 mA @
1MHz
N01L1618N1AT2 44 - TSOP II Green
Pin Configurations
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A15
A14
A13
A12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
PIN
ONE
44 A5
43 A6
42 A7
41 OE
40 UB
39 LB
38 I/O15
37 I/O14
36 I/O13
35 I/O12
34 VSS
33 VCC
32 I/O11
31 I/O10
30 I/O9
29 I/O8
28 NC
27 A8
26 A9
25 A10
24 A11
23 NC
123456
A LB OE A0
B I/O8 UB A3
C I/O9 I/O10 A5
A1 A2 NC
A4 CE I/O0
A6 I/O1 I/O2
D VSS I/O11 NC A7 I/O3 VCC
E VCC I/O12 NC NC I/O4 VSS
F I/O14 I/O13 A14 A15 I/O5 I/O6
G I/O15 NC A12 A13 WE I/O7
H NC A8 A9 A10 A11 NC
48 Pin BGA (top)
6 x 8 mm
Pin Descriptions
Pin Name
A0-A15
WE
CE
OE
LB
UB
I/O0-I/O15
NC
VCC
VSS
Pin Function
Address Inputs
Write Enable Input
Chip Enable Input
Output Enable Input
Lower Byte Enable Input
Upper Byte Enable Input
Data Inputs/Outputs
Not Connected
Power
Ground
(DOC# 14-02-009 REV F ECN# 01-0995)
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
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NanoAmp Solutions, Inc.
Functional Block Diagram
Address
Inputs
A0 - A3
Word
Address
Decode
Logic
Address
Inputs
A4 - A15
Page
Address
Decode
Logic
CE
WE
OE
UB
Control
Logic
LB
4K Page
x 16 word
x 16 bit
RAM Array
N01L1618N1Awww.DataSheet4U.com
Input/
Output
Mux
and
Buffers
I/O0 - I/O7
I/O8 - I/O15
Functional Description
CE WE OE UB LB
I/O0 - I/O151
MODE
POWER
HXXXX
L XXHH
L L X3 L1 L1
L H L L1 L1
L H H L1 L1
High Z
High Z
Data In
Data Out
High Z
Standby2
Active
Write3
Read
Active
Standby
Active
Active -> Standby4
Active -> Standby4
Standby4
1. When UB and LB are in select mode (low), I/O0 - I/O15 are affected as shown. When LB only is in the select mode only I/O0 - I/O7
are affected as shown. When UB is in the select mode only I/O8 - I/O15 are affected as shown.
2. When the device is in standby mode, control inputs (WE, OE, UB, and LB), address inputs and data input/outputs are internally
isolated from any external influence and disabled from exerting any influence externally.
3. When WE is invoked, the OE input is internally disabled and has no effect on the circuit.
4. The device will consume active power in this mode whenever addresses are changed. Data inputs are internally isolated from any
external influence.
Capacitance1
Item
Symbol
Test Condition
Input Capacitance
I/O Capacitance
CIN VIN = 0V, f = 1 MHz, TA = 25oC
CI/O VIN = 0V, f = 1 MHz, TA = 25oC
1. These parameters are verified in device characterization and are not 100% tested
Min Max Unit
8 pF
8 pF
(DOC# 14-02-009 REV F ECN# 01-0995)
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
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NanoAmp Solutions, Inc.
N01L1618N1Awww.DataSheet4U.com
Absolute Maximum Ratings1
Item
Symbol
Rating
Unit
Voltage on any pin relative to VSS
Voltage on VCC Supply Relative to VSS
Power Dissipation
Storage Temperature
Operating Temperature
Soldering Temperature and Time
VIN,OUT
VCC
PD
TSTG
TA
TSOLDER
–0.3 to VCC+0.3
–0.3 to 3.0
500
–40 to 125
-40 to +85
260oC, 10sec
V
V
mW
oC
oC
oC
1. Stresses greater than those listed above may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operating section of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Operating Characteristics (Over Specified Temperature Range)
Item
Symbol
Test Conditions
Min.
Typ1
Max Unit
Supply Voltage
VCC
1.65 1.8
2.2 V
Data Retention Voltage
VDR Chip Disabled3
1.2
V
Input High Voltage
VIH
0.7VCC
VCC+0.3 V
Input Low Voltage
VIL
–0.3
0.3VCC V
Output High Voltage
VOH
IOH = 0.2mA
VCC–0.3
V
Output Low Voltage
VOL IOL = -0.2mA
0.3 V
Input Leakage Current ILI VIN = 0 to VCC
0.5 µA
Output Leakage Current
ILO OE = VIH or Chip Disabled
0.5 µA
Read/Write Operating Supply Current
@ 1 µs Cycle Time2
ICC1
VCC=2.2 V, VIN=VIH or VIL
Chip Enabled, IOUT = 0
0.7 3.0 mA
Read/Write Operating Supply Current
@ 85 ns Cycle Time2
ICC2
VCC=2.2 V, VIN=VIH or VIL
Chip Enabled, IOUT = 0
8 16 mA
Page Mode Operating Supply Current
@ 85ns Cycle Time2 (Refer to Power
Savings with Page Mode Operation
ICC3
VCC=2.2 V, VIN=VIH or VIL
Chip Enabled, IOUT = 0,
3
mA
diagram)
Read/Write Quiescent Operating Sup-
ply Current3
ICC4
VCC=2.2 V, VIN=VIH or VIL
Chip Enabled, IOUT = 0,
f=0
20 µA
Maximum Standby Current3
VIN = VCC or 0V
ISB1 Chip Disabled
tA= 85oC, VCC = 2.2 V
0.5 10 µA
Maximum Data Retention Current3
IDR
VCC = 1.2V, VIN = VCC or 0
Chip Disabled, tA= 85oC
5 µA
1. Typical values are measured at Vcc=Vcc Typ., TA=25°C and are not 100% tested.
2. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current required to drive
output capacitance expected in the actual system.
3. This device assumes a standby mode if the chip is disabled (CE high). In order to achieve low standby current all inputs must be
within 0.2 volts of either VCC or VSS
(DOC# 14-02-009 REV F ECN# 01-0995)
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
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NanoAmp Solutions, Inc.
N01L1618N1Awww.DataSheet4U.com
Power Savings with Page Mode Operation (WE = VIH)
Page Address (A4 - A15 )
Word Address (A0 - A3)
CE
Word 1
Open page
Word 2
...
Word 16
OE
LB, UB
Note: Page mode operation is a method of addressing the SRAM to save operating current. The internal
organization of the SRAM is optimized to allow this unique operating mode to be used as a valuable power
saving feature.
The only thing that needs to be done is to address the SRAM in a manner that the internal page is left open
and 16-bit words of data are read from the open page. By treating addresses A0-A3 as the least significant
bits and addressing the 16 words within the open page, power is reduced to the page mode value which is
considerably lower than standard operating currents for low power SRAMs.
(DOC# 14-02-009 REV F ECN# 01-0995)
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
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