DatasheetBay.com



DEI1016 (Device Engineering) : Total 17 Pages

No Preview Available !

[ Download PDF for PC ]

Device
www.DaEtaSnheegt4Ui.ncomeering
Incorporated
385 East Alamo Drive
Chandler, AZ 85225
Phone: (480) 303-0822
Fax: (480) 303-0824
E-mail: info@deiaz.com
DEI1016/DEI1016A/DEI1016B
/DEI1016C ARINC 429
Transceiver Family
Features
Two Receivers and One Transmitter
Industry Standard Pin for Pin Replacement Part
Wraparound Self-Test mode
Word length can be configured for 25 bit or 32 bits operation
Parity Status and generation of Receive and Transmit Words
8 Word Transmitter buffer
Low Power CMOS processing
Supports multiple ARINC protocols: 429, 571, 575, 706
Available in extended (-55/+85°C) and Military (-55/+125°C) temperature ranges
General Description:
The DEI1016 provides an interface between a standard avionics type serial digital data bus and a 16-bit-wide digital data bus. The
interface circuit consists of a single channel transmitter with an 8X32 bit buffer, two independent receive channels, and a host
programmable control register to select operating options. The two receiver channels operate identically, each providing a direct
electrical interface to an ARINC data bus.
The transmitter circuit contains an 8 word by 32 bit buffer memory and control logic which allows the host to write a block of data
into the transmitter. The block of data is transmitted automatically by enabling the transmitter with no further attention by the host
computer. Data is transmitted in TTL format on the D0(A)/D0(B) output pins. The signal format is compatible with DEI’s extensive
line of ARINC 429 Line drivers for easy connection to the ARINC data bus.
ARINC 429
Receive 0
ARINC 429
Receive 1
ARINC 429
Transmit
© 2005 Device Engineering Inc.
Receive
Decoder
Receive
Decoder
Transmit
Encoder
32
Control
Register
32
32
16
Host
Interface
32
TX FIFO
8 Words X 32 Bits
/DR1, /DR2
TXR
/OE1, /OE2
/LD1, /LD2
ENTX
/LDCW
/DBCEN
/MR
16 DATA BUS
Figure 1: DEI1016 Block Diagram
Page 1 of 17
DS-MW-01016-01 Rev A
01/07/2005



No Preview Available !

[ Download PDF for PC ]

Table 1: DEI 1016 Absolute Maximum Ratings
www.DataSheet4U.com
PARAMETER
SYMBOL
MIN
Supply Voltage
DC Input Voltage (except pins DI1(A,B) and DI2(A,B))
Voltage at pins DI1(A,B) and DI2(A,B)
Clamp diode current, any pin except DI inputs
VDD -0.5
VIN -0.6
VIN
DC Output Current per pin
DCV or GND current per pin
Storage Temperature
TSTG
-65
Junction Temperature, operating
TJmax
Lead Temperature (soldering, 10 sec)
TLead
1MCK Clock Frequency
MAX
+7.0
VCC + 0.6
±29
±25
±25
±50
+150
+145
+275
1.16
UNITS
V
V
V
mA
mA
mA
°C
°C
°C
MHz
Table 2: DEI 1016 DC Electrical Characteristics
Unless noted, operating conditions: VDD = 5V ± 10%, Extended Temp Devices: Ta = -55ºC to +85ºC, Military Temp Devices: Ta = -55ºC
to +125ºC
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
ARINC LINE INPUTS
Logic 1 Input Voltage
Logic 0 Input Voltage
Null Input Voltage
Common Mode Voltage
VIH
VIL
VNUL
VCM
VDIFF DI(A) and DI(B)
VDIFF DI(A) and DI(B)
VDIFF DI(A) and DI(B)
6.5 10 13
-6.5 -10 -13
-2.5 0 +2.5
-5 +5
V
V
V
V
Differential Input Impedance
RI
12 k
Input Impedance to VDD
RH
12 k
Input Impedance to GND
RG
12 k
Differential Input Capacitance
Input Capacitance to VDD
Input Capacitance to GND
CI
CH
CG
LOGIC INPUTS (including bi-directional)
20 pF
20 pF
20 pF
Low Level Input Voltage
High Level Input Voltage
Input Leakage Current
VIL
VIH
IIN VIN = GND to VDD
0.8 V
2.0 V
-10 +10 µA
Input Capacitance
CIN
LOGIC OUTPUTS (including bi-directional)
15 pF
High Level Output Voltage
VOH IOH = 20µA (CMOS)
IOH = 6mA (TTL)
VDD – 0.1
2.7
V
Low Level Output Voltage
VOL IOL = 20µA (CMOS)
IOL = 6mA (TTL)
0.1 V
0.4
POWER SUPPLY INPUT
Supply Current
Supply Voltage
IDD 1MCK = 1MHz
VDD
5 10 mA
4.5 5 5.5 VDC
© 2005 Device Engineering Inc.
Page 2 of 17
DS-MW-01016-01 Rev A
01/07/2005



No Preview Available !

[ Download PDF for PC ]

Table 3: DEI 1016 AC Electrical Characteristics
www.DataSheet4U.com
PARAMETER
1MCK Frequency
1MCK Duty Cycle
1MCK Rise/Fall Time
Master Reset Pulse Width
Transmitter Data Rate (1MCK = 1MHz)
Receiver Data Rate (1MCK = 1MHz),(DATA = 50% BIT/
50% NULL TIME)
SYMBOL
f1MCK
CKDC
TCRF
TMR
TDR
RDR
Data Rate
100kbps
MIN
40
200
99
95
MAX
1.01
60
10
101
105
Data Rate
12.5kbps
MIN
40
200
12.4
8.0
MAX
1.01
60
10
12.6
14.5
UNITS
MHz
%
ns
ns
kbps
kbps
Table 4: Pin Definitions
SYMBOL
DEFINITION
VDD
GND
DI1(A)
DI1(B)
DI2(A)
DI2(B)
/DR1
/DR2
SEL
/OE1
/OE2
D[15:0]
/LD1
/LD2
TXR
DO(A)
DO(B)
ENTX
/LDCW
1MCK
TXCK
/MR
/DBCEN
Power Input. +5VDC ±10%
Power Return and Signal Ground.
ARINC 429 Input. Receiver Channel 1, “A” input
ARINC 429 Input. Receiver Channel 1, “B” input
ARINC 429 Input. Receiver Channel 2, “A” input
ARINC 429 Input. Receiver Channel 2, “B” input
Logic Output. Data Ready, Receiver 1. A Low output indicates valid data in receiver 1.
Logic Output. Data Ready, Receiver 2. A Low output indicates valid data in receiver 2.
Logic Input. Receiver word select. A Low input selects receiver Word 1; Hi selects Word 2 to be read on D[15:0] port.
Logic Input. Receiver 1 Output Enable. A Low input enables the D[15:0] port to output Receiver 1 data. Word 1 or
Word 2 will be output as determined by the SEL input.
Logic Input. Receiver 2 Output Enable. A Low input enables the D[15:0] port to output Receiver 2 data. Word 1 or
Word 2 will be output as determined by the SEL input.
Logic Input / Tri-state Output. This 16-bit bi-directional data port is the uP data interface. Receiver data is read from
this port. Control Register and Transmitter FIFO data is written into this port.
Logic Input. Load Transmitter Word 1. A Low input pulse loads Word 1 into the Transmitter FIFO from D[15:0].
Logic Input. Load Transmitter Word 2. A Low input pulse loads Word 2 into the Transmitter FIFO from D[15:0].
Logic Output. Transmitter Ready. A Hi output indicates the Transmitter FIFO is empty and ready to accept new data.
Logic Output. Transmitter serial data ‘A’ output. This is a return-to-zero format signal which will normally feed an
ARINC 429 Line Driver IC. A Hi output indicates the Transmitter data bit is a 1. The signal returns to zero for
second half of bit time.
Logic Output. Transmitter serial data ‘B’ output. This is a return-to-zero format signal which will normally feed an
ARINC 429 Line Driver IC. A Hi output indicates the Transmitter data bit is a 0. The signal returns to zero for
second half of bit time.
Logic Input. Enable Transmitter. A Hi input enables the Transmitter to send data from the Transmitter FIFO. This
must be Low while writing data into Transmitter FIFO. Transmitter memory is cleared by high-to-low transition.
Logic Input. Load Control Register. A Low input pulse loads the Control Register from D[15:0].
Logic Input. External Clock. Master clock used by both the Receivers and Transmitter. The 1MHz rate is a X10 clock
for the HI data rate (100 kbps), and a X80 clock for LO data rate (12.5 kbps).
Logic Output. Transmitter Clock. This outputs a clock frequency equal to the transmit data rate. The clock is always
enabled and in phase with the data. The output is Hi during the first half of the data bit time.
Logic Input. Master Reset. A Lo input resets the Transmitter FIFO, bit counters, word counter, gap timers, /DRx, and
TXR. The Control Register is not affected. Used on power up and system reset.
Logic Input with internal pull up to VDD. Data Bit Control Enable. A Low input enables the transmitter parity bit
control function as defined by control register bit 4 (PAREN). A Hi input forces transmitter parity bit insertion
regardless of PAREN value. The pin is normally left open or tied to ground.
© 2005 Device Engineering Inc.
Page 3 of 17
DS-MW-01016-01 Rev A
01/07/2005



No Preview Available !

[ Download PDF for PC ]

wwwF.DuantacSthieoent4aUl.cDomescription:
The DEI 1016 supports a number of various options
which are selected by data written into the control
register. Data is written into the control register from the
16-bit data bus when the /LDCW signal is pulsed to a
logic “0”. The twelve control bits control the following
functions:
1) Word Length (32 or 25 bits)
2) Transmitter bit 32 (Parity or Data)
3) Wrap around self test.
4) Source Destination code checking of received data.
5) Transmitter parity (even or odd)
6) Transmitter and Receiver data rate (100 or 12.5 kbps)
Table 5: Control Register Format
BIT SYMBOL BIT SYMBOL
D15 (MSB) WLSEL
D7 X1
D14 RCVSEL
D6 SDENB1
D13 TXSEL
D5 /SLFTST
D12 PARCK
D4 PAREN
D11 Y2
D3 NOT USED
D10 X2
D2 NOT USED
D9 SDENB2 D1 NOT USED
D8 Y1 D0 NOT USED
Table 6: DEI1016 Control Word
NAME
PAREN
DATA BIT
DESCRIPTION
Transmitter Parity Enable. Enables parity bit insertion into transmitter data bit 32. Parity is always
D4 inserted if /DBCEN is open or HI. If /DBCEN is LO, Logic “0” on PAREN inserts data on bit 32, and
Logic “1” on PAREN inserts parity on bit 32.
/SLFTST1
Self Test Enable. Logic “0” enables a “wrap around” test mode which internally connects the transmitter
D5
outputs to both receiver inputs, bypassing the receiver front end. The test data is inverted before going
into receiver 2 so that its data is the complement of that received by receiver 1. The transmitter output is
active during test mode.
SDEN12
X1, Y12
D6
D7, D8
S/D Code Check Enable for receiver 1. Logic “1” enables the Source/Destination Decoder for receiver 1.
S/D compare code RX1. If the receiver 1 S/D code check is enabled (SDENB1=1), then incoming
receiver data S/D fields will be compared to X1, Y1. If they match, the word will be accepted by receiver
1; if not, it will be ignored. X1 (D7) is compared to serial data bit 9, Y1 (D8) is compared to serial data
bit 10.
SDEN22
X2, Y22
D9 S/D Code Check Enable for receiver 1. Logic “1” enables the Source/Destination Decoder for receiver 1.
S/D compare code RX2. If the receiver 2 S/D code check is enabled (SDENB2=1), then incoming
D10, D11
receiver data S/D fields will be compared to X2, Y2. If they match, the word will be accepted by receiver
2; if not, it will be ignored. X2 (D10) is compared to serial data bit 9, Y2 (D11) is compared to serial
data bit 10.
PARCK
D12
Parity Check Enable. Logic “1” inverts the transmitter parity bit for test of parity circuits. Logic “0”
selects normal odd parity; logic “1” selects even parity.
TXSEL3
Transmitter Data Rate Select. Logic “0” sets the transmitter to the HI data rate. HI rate is equal to the
D13 clock rate divided 10. Logic “1” sets the transmitter to the LO data rate. LO rate is equal to the clock rate
divided by 80.
RCVSEL4
Receiver Data Rate Select. Logic “0” sets both receivers to accept the HI data rate. The nominal HI data
D14 rate is the input clock divided by 10. Logic “1” sets both receivers to the LO data rate. The nominal LO
data rate is the input clock divided by 80.
WLSEL5
D15
Word Length Select. Logic “0” sets the transmitter and receivers to a 32 bit word format. Logic ”1” sets
them to a 25 bit word format.
NOT USED
D0-D3
When writing to the control register, the four “not used bits” are “don’t care” bits. These four bits will not
be used on the chip.
NOTES
1) The test mode should always conclude with ten null’s. This step prevents both receivers from accepting invalid data.
2) SDENBn, Xn & Yn should be changed within 20 bit times after /DRn goes low and the bit stream has been read, or within 30 bit times after a
master reset has been removed.
3) TXSEL should only be changed during the time that TXR is high or Master Reset is low.
4) RCVSEL should be changed only during a Master Reset pulse. If changed at any other time, then the next bit stream from both Receiver 1 and
Receiver 2 should be ignored.
5) When the control word is written the effect of the WLSEL bit will take effect immediately on the first complete ARINC word received or
transmitted following the control word write operation.
© 2005 Device Engineering Inc.
Page 4 of 17
DS-MW-01016-01 Rev A
01/07/2005





[ Download PDF for PC ]





0  1  2  3  4  5  6  7  8  9  A  B  C  D  E  F  G  H  I  J  K  L  M  N  O  P  Q  R  S  T  U  V  W  X  Y  Z  

This is a individually operated, non profit site. If this site is good enough to show, please introduce this site to others.
* 2015 :: DatasheetBay.com :: DatasheetBay