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DEI1016 (Device Engineering) : Total 13 Pages

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Devicewww.DataSheet4U.com
Engineering
Incorporated
430 S. Rockford Dr.
Tempe, AZ 85281
Phone: (480) 303-0822
Fax: (480) 303-0824
E-mail: info@deiaz.com
DEI 1016
ARINC 429 Transceiver
Features
Two Receivers and One Transmitter
Harris/Holt/Raytheon Pin for Pin Replacement
Wraparound Self-Test mode
Word length of 25 or 32 bits
Parity Status and generation of Receive and Transmit Words
8 Word Transmitter buffer
Low Power CMOS processing
Supports multiple ARINC data busses: 429, 571, 575, 706.
General Description:
The DEI 1016 provides an interface between a standard avionics type serial digital data bus and a 16-bit-wide
digital data bus. The interface circuit consists of a single channel transmitter with an 8X32 bit buffer, two inde-
pendent receive channels, and a host programmable control register to select operating options. The two re-
ceiver channels operate identically, each providing a direct electrical interface to an ARINC data bus.
The transmitter circuit contains an 8 word by 32 bit buffer memory and control logic which allows the host to
write a block of data into the transmitter. The block of data is transmitted automatically by enabling the trans-
mitter with no further attention by the host computer. Data is transmitted in TTL format on the D0(A)/D0(B) out-
put pins. The signal format is compatible with DEI’s extensive line of ARINC 429 Line drivers for easy connec-
tion to the ARINC data bus.
ARINC 429
Receive 0
ARINC 429
Receive 1
ARINC 429
Transmit
© Device Engineering Inc.
Tempe, Arizona
Receive
Decoder
Receive
Decoder
Transmit
Encoder
32 bit
Control
Register
32 bit
32 bit
16 bit
Host
Interface
32 bit
16 bit
/DR1or/DR2
TXR
/OE1 or /OE2
/LD1 or /LD2
ENTX
/LDCW
/DBCEN
/MR
DATA BUS
TX FIFO
8 Words X 32 Bits
Figure 1: DEI1016 Block Diagram
Page 1 of 13
DEI1016 Rev. C
July 20, 2000



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Table 1: DEI 1016 Absolute Maximum Ratings
PARAMETER
SYMBOL
MIN
Supply Voltage
DC Input Voltage (except pins DI1(A,B) and DI2(A,B))
Voltage at pins DI1(A,B) and DI2(A,B)
VDD -0.5
VIN -0.3
VIN -29
DC Output Current per pin
-25
DCV or GND current per pin
-50
Storage Temperature
Operating Temperature
1MCK Clock Frequency
TSTG
TO
-65
-55
MAX
+7.0
VCC + 0.3
+29
+25
+50
+150
+125
1.16
UNITS
V
V
V
mA
mA
°C
°C
MHz
Table 2: DEI 1016 DC Electrical Characteristics
Unless noted, operating connections: VDD = 5V ± 10%, T = -40ºC ~ +85ºC
PARAMETER
SYMBOL
CONDITIONS
MIN TYP
ARINC LINE INPUTS
Logic 1 Input Voltage
Logic 0 Input Voltage
VIH VDIFF DI(A) and DI(B)
VIL VDIFF DI(A) and DI(B)
6.5 10
-6.5 -10
Null Input Voltage
Common Mode Voltage
VNUL
VCM
VDIFF DI(A) and DI(B)
-2.5 0
Differential Input Impedance
RI
12
Input Impedance to VDD
RH
12
Input Impedance to GND
RG
12
Differential Input Capacitance
Input Capacitance to VDD
Input Capacitance to GND
CI
CH
CG
ALL OTHER INPUTS (including bi-directional)
Max low level Input Voltage
Min high level Input Voltage
Max Input Current
VIL
VIH
IIN VIN = GND to VDD
2
Input Capacitance
CIN
ALL OUTPUTS (including bi-directional)
Min High level output voltage
VOH IOH = 20µA (CMOS)
IOH = 6mA (TTL)
VDD –0.1
2.7
Max Low level output voltage
VOL IOL = 20µA (CMOS)
IOL = 6mA (TTL)
POWER SUPPLY INPUT
Supply Current
Supply Voltage
IDD 1MCK = 1MHz
VDD
5
4.5 5
MAX UNITS
13
-13
+2.5
±5
20
20
20
V
V
V
V
k
k
k
pF
pF
pF
0.8 V
V
±10 µA
15 pF
V
0.1 V
0.4
10 mA
5.5 VDC
© Device Engineering Inc.
Tempe, Arizona
Page 2 of 13
DEI1016 Rev. C
July 20, 2000



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Table 3: DEI 1016 AC Electrical Characteristics
Data Rate
100kbps
Data Rate
12.5kbps
PARAMETER
SYMBOL MIN MAX MIN MAX
1MCK Frequency
f1MCK
1.01 1.01
1MCK Duty Cycle
CKDC 40 60 40 60
1MCK Rise/Fall Time
TCRF
10 10
Master Reset Pulse Width
TMR 200
200
Transmitter Data Rate (1MCK = 1MHz)
TDR
99 101 12.4 12.6
Receiver Data Rate (1MCK = 1MHz)
RDR 95 105 9.0 14.5
UNITS
MHz
%
ns
ns
kbps
kbps
Table 4: Pin Definitions
SYMBOL
DEFINITION
VDD +5VDC ±10%; Power Supply
DI1(A) Data In 1, HI ( Input, ARINC 429 compatible ) ARINC 429 “A” data input to receiver 1.
DI1(B) Data In 1, LO ( Input, ARINC 429 compatible ) ARINC 429 “B” data input to receiver 1.
DI2(A)
DI2(B)
/DR1
/DR2
Data In 2, HI ( Input, ARINC 429 compatible ) ARINC 429 “A” data input to receiver 2.
Data In 2, LO ( Input, ARINC 429 compatible ) ARINC 429 “B” data input to receiver 2.
Data Ready Receiver 1. (Output, active low) Logic “0” indicates valid data in receiver 1.
Data Ready Receiver 2. (Output, active low) Logic “0” indicates valid data in receiver 2.
SEL
/OE1
Receiver data select. Selects receiver word 1 or 2 to be read by the data bus.
Receiver 1 data enable. (input, active Low). Logic “0” enables selected data from receiver 1 on to the
data bus.
/OE2 Receiver 2 data enable. (input, active Low). Logic “0” enables selected data from receiver 2 on to the
data bus.
D0-D15
/LD1
/LD2
16-bit Data Bus (bi-directional, tri-state) Bi-directional data bus for reading data from either receivers, or
for writing data into the transmitter memory or control register.
Load Transmitter word 1 (input, active Low) Logic “0” pulse loads word 1 into the transmitter memory
from data bus.
Load Transmitter word 2 (input, active Low) Logic “0” pulse loads word 2 into the transmitter memory
from data bus.
TXR
DO(A)
DO(B)
ENTX
Transmitter Ready (output, active High) Logic “1” indicates the transmitter memory is empty and ready
to accept new data.
Transmitter Data, HI (output, active High, return to zero) Logic “1” indicates transmitter data bit is a 1.
The signal returns to zero for second half of bit time.
Transmitter Data, LO (output, active High, return to zero) Logic “1” indicates transmitter data bit is a “0“.
The signal returns to zero for second half of bit time.
Enable Transmitter (input, active High) Logic “1” enables transmitter to send data from transmitter mem-
ory. This must be logic “0” while writing data into transmitter memory. Transmitter memory is cleared
by high-to-low transition.
/LDCW Load Control Register (input, active Low) Logic “0” pulse loads control register from the data bus.
1MCK
TXCK
/MR
External Clock (input, TTL compatible) Master clock used by both the receivers and transmitter. The
1MHz rate is a X10 clock for the HI data rate (100 kbps), and a X80 clock for LO data rate (12.5 kbps)
Transmitter Clock (output) Delivers a clock frequency equal to the transmit data rate. The clock is al-
ways enabled and in phase with the data. The clock is a logic “1” during the first half of the data bit time.
Master Reset (input, active Low pulse) Logic “0” resets transmitter memory, bit counters, word counter,
gap timers, /DRx, and TXR. Used on power up and system reset.
/DBCEN Data Bit Control Enable (input, active low with internal pull up to VDD) Logic “0” enables the transmitter
parity bit control function as defined by control register bit 4 (PAREN). Logic “1” forces transmitter parity
bit insertion regardless of PAREN value. Pin is normally left open or tied to ground.
© Device Engineering Inc.
Tempe, Arizona
Page 3 of 13
DEI1016 Rev. C
July 20, 2000



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Functional Description:
wwwT.DhaetaDShEeIet140U1.c6omsupports a number of various options which
are selected by data written into the control register. Data
is written into the control register from the 16-bit data bus
when the /LDCW signal is pulsed to a logic “0”. The twelve
control bits control the following functions:
1) Word Length (32 or 25 bits)
2) Transmitter bit 32 (Parity or Data)
3) Wrap around self test.
4) Source Destination code checking of received data.
5) Transmitter parity (even or odd)
6) Transmitter and Receiver data rate (100 or 12.5 kbps)
Table 5: Control Register Format
BIT SYMBOL BIT SYMBOL
D15 (MSB) WLSEL D7
X1
D14 RCVSEL D6
SDENB1
D13
TXSEL
D5
/SLFTST
D12 PARCK D4
PAREN
D11 Y2
D3 NOT USED
D10 X2
D2 NOT USED
D9 SDENB2 D1 NOT USED
D8 Y1 D0 NOT USED
Table 6: DEI 1016 Control Word
NAME DATA BIT
DESCRIPTION
PAREN D4
Transmitter Parity Enable. Enables parity bit insertion into transmitter data bit 32. Parity is
always inserted if /DBCEN is open or HI. If /DBCEN is LO, Logic “0” on PAREN inserts data
on bit 32, and Logic “1” on PAREN inserts parity on bit 32.
/SLFTST1 D5
Self Test Enable. Logic “0” enables a “wrap around” test mode which internally connects the
transmitter outputs to both receiver inputs, bypassing the receiver front end. The test data is
inverted before going into receiver 2 so that its data is the complement of that received by re-
ceiver 1. The transmitter output is active during test mode.
SDEN12 D6
S/D Code Check Enable for receiver 1. Logic “1” enables the Source/Destination Decoder for
receiver 1.
X1, Y12 D7, D8
S/D compare code RX1. If the receiver 1 S/D code check is enabled (SDENB1=1), then in-
coming receiver data S/D fields will be compared to X1, Y1. If they match, the word will be
accepted by receiver 1; if not, it will be ignored. X1 (D7) is compared to serial data bit 9, Y1
(D8) is compared to serial data bit 10.
SDEN22 D9
S/D Code Check Enable for receiver 1. Logic “1” enables the Source/Destination Decoder for
receiver 1.
X2, Y22
D10, D11
S/D compare code RX2. If the receiver 2 S/D code check is enabled (SDENB2=1), then in-
coming receiver data S/D fields will be compared to X2, Y2. If they match, the word will be
accepted by receiver 2; if not, it will be ignored. X2 (D10) is compared to serial data bit 9, Y2
(D11) is compared to serial data bit 10.
PARCK D12
Parity Check Enable. Logic “1” inverts the transmitter parity bit for test of parity circuits. Logic
“0” selects normal odd parity; logic “1” selects even parity.
TXSEL3 D13
Transmitter Data Rate Select. Logic “0” sets the transmitter to the HI data rate. HI rate is
equal to the clock rate divided 10. Logic “1” sets the transmitter to the LO data rate. LO rate
is equal to the clock rate divided by 80.
RCVSEL4 D14
Receiver Data Rate Select. Logic “0” sets both receivers to accept the HI data rate. The
nominal HI data rate is the input clock divided by 10. Logic “1” sets both receivers to the LO
data rate. The nominal LO data rate is the input clock divided by 80.
WLSEL5 D15
Word Length Select. Logic “0” sets the transmitter and receivers to a 32 bit word format.
Logic ”1” sets them to a 25 bit word format.
NOT
USED
D0-D4
When writing to the control register, the four “not used bits” are “don’t care” bits. These four
bits will not be used on the chip.
NOTES:
1)The test mode should always conclude with ten null’s. This step prevents both receivers from accepting invalid data.
2)SDENBn, Xn & Yn should be changed within 20 bit times after /DRn goes low and the bit stream has been read, or within 30 bit
times after a master reset has been removed.
3)TXSEL should only be changed during the time that TXR is high or Master Reset is low.
4)RCVSEL should be changed only during a Master Reset pulse. If changed at any other time, then the next bit stream from both
Receiver 1 and Receiver 2 should be ignored.
5)When the control word is written the effect of the WLSEL bit will take effect immediately on the first complete ARINC word re-
ceived or transmitted following the control word write operation.
© Device Engineering Inc.
Tempe, Arizona
Page 4 of 13
DEI1016 Rev. C
July 20, 2000





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