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ADT7310 (Analog Devices) : Total 24 Pages

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±0.5°C Accurate, 16-Bit
Digital SPI Temperature Sensor
ADT7310
FEATURES
13- or 16-bit user selectable temperature-to-digital converter
Temperature accuracy ±0.5°C from −40°C to +105°C
No temperature calibration/correction required by user
Power saving 1 sample per second (SPS) mode
Fast first conversion on power-up of 6 ms
SPI-compatible interface
Operating temperature from −55°C to +150°C
Operating voltage: 2.7 V to 5.5 V
Critical overtemperature indicator
Programmable overtemperature/undertemperature interrupt
Low power consumption: 700 μW typical at 3.3 V
Shutdown mode for lower power: 7μW typical at 3.3 V
8-lead narrow SOIC RoHS-compliant package
APPLICATIONS
Medical equipment
Environmental control systems
Computer thermal monitoring
Thermal protection
Industrial process control
Power system monitors
Hand-held applications
GENERAL DESCRIPTION
The ADT7310 is a high accuracy digital temperature sensor
in a narrow SOIC package. It contains a band gap temperature
reference and a 13-bit ADC to monitor and digitize the
temperature to a 0.0625°C resolution. The ADC resolution,
by default, is set to 13 bits (0.0625 °C). This can be changed
to 16 bits (0.0078 °C) by setting Bit 7 in the configuration
register (Register Address 0x01).
The ADT7310 is guaranteed to operate over supply voltages from
2.7 V to 5.5 V. Operating at 3.3 V, the average supply current is
typically 210 μA. The ADT7310 has a shutdown mode that
powers down the device and offers a shutdown current of
typically 2 μA. The ADT7310 is rated for operation over the
−55°C to +150°C temperature range.
The CT pin is an open-drain output that becomes active when
the temperature exceeds a programmable critical temperature
limit. The default critical temperature limit is 147°C. The INT
pin is also an open-drain output that becomes active when the
temperature exceeds a programmable limit. The INT and CT
pins can operate in either comparator or interrupt mode.
SCLK 1
DOUT 2
DIN 3
CS 4
TEMPERATURE
VALUE
REGISTER
THYST
REGISTER
THIGH
REGISTER
FUNCTIONAL BLOCK DIAGRAM
INTERNAL
REFERENCE
INTERNAL
OSCILLATOR
CONFIGURATION
AND STATUS
REGISTERS
TEMPERATURE
SENSOR
TCRIT
REGISTER
TLOW
REGISTER
Σ-Δ
MODULATOR
FILTER
LOGIC
Figure 1.
ADT7310
TCRIT
THIGH
6 CT
5 INT
TLOW
7 GND
8 VDD
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.



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TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
SPI Timing Specifications ........................................................... 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ........................................................................ 9
Circuit Information...................................................................... 9
Converter Details.......................................................................... 9
Temperature Measurement ......................................................... 9
One-Shot Mode .......................................................................... 10
1 SPS Mode.................................................................................. 10
Continuous Read Mode............................................................. 12
Shutdown..................................................................................... 12
Fault Queue ................................................................................. 12
Temperature Data Format ......................................................... 13
Temperature Conversion Formulas ......................................... 13
Registers ........................................................................................... 14
REVISION HISTORY
4/09—Revision 0: Initial Version
Status Register............................................................................. 14
Configuration Register .............................................................. 15
Temperature Value Register ...................................................... 16
ID Register................................................................................... 16
TCRIT Setpoint Register ............................................................... 16
THYST Setpoint Register............................................................... 17
THIGH Setpoint Register .............................................................. 17
TLOW Setpoint Register ............................................................... 17
Serial Interface ................................................................................ 18
SPI Command Byte.................................................................... 18
Writing Data ............................................................................... 19
Reading Data............................................................................... 20
Interfacing to DSPs or Microcontrollers ................................. 20
Serial Interface Reset.................................................................. 20
INT and CT Outputs...................................................................... 21
Undertemperature and Overtemperature Detection ............ 21
Applications Information .............................................................. 23
Thermal Response Time ........................................................... 23
Supply Decoupling ..................................................................... 23
Temperature Monitoring........................................................... 23
Outline Dimensions ....................................................................... 24
Ordering Guide .......................................................................... 24
Rev. 0 | Page 2 of 24



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ADT7310
SPECIFICATIONS
TA = −55°C to +150°C; VDD = 2.7 V to 5.5 V; unless otherwise noted.
Table 1.
Parameter
Min Typ Max Unit
TEMPERATURE SENSOR AND ADC
Accuracy1
±0.5 °C
±0.7 °C
±0.8 °C
±1.0 °C
ADC Resolution
13 Bits
16 Bits
Temperature Resolution
13 Bit
16 Bit
Temperature Conversion Time
Fast Temperature Conversion
Time
1 SPS Conversion Time
Temperature Hysteresis
Repeatability
DC PSRR
DIGITAL OUTPUTS (OPEN DRAIN)
High Output Leakage Current, IOH
Output High Current
Output Low Voltage, VOL
Output High Voltage, VOH
Output Capacitance, COUT
DIGITAL INPUTS
Input Current
Input Low Voltage, VIL
Input High Voltage, VIH
Pin Capacitance
DIGITAL OUTPUT (DOUT)
Output High Voltage, VOH
Output Low Voltage, VOL
Output Capacitance, COUT
POWER REQUIREMENTS
Supply Voltage
Supply Current
At 3.3 V
At 5.5 V
1 SPS Current
At 3.3V
At 5.5V
Shutdown Current
At 3.3 V
At 5.5 V
Power Dissipation Normal Mode
Power Dissipation 1 SPS
0.7 × VDD
0.7 × VDD
VOH − 0.3
2.7
0.0625
0.0078
240
6
60
0.02
0.01
0.1
0.1
3
5
210
230
46
65
2.0
4.4
700
150
°C
°C
ms
ms
ms
°C
°C
°C/V
5 μA
1 mA
0.4 V
V
pF
±1 μA
0.4 V
V
10 pF
V
0.4 V
50 pF
5.5 V
250 μA
300 μA
μA
μA
15 μA
25 μA
μW
μW
Test Conditions/Comments
TA = −40°C to +105°C, VDD = 2.7 V to 3.6 V
TA = −55°C to +150°C, VDD = 2.7 V to 3.6 V
TA = −40°C to +105°C, VDD = 4.5 V to 5.5 V
TA = −55°C to +150°C, VDD = 2.7 V to 5.5 V
Twos complement temperature value of sign bit plus 12 ADC bits
(power-up default resolution)
Twos complement temperature value of sign bit plus 15 ADC bits
(Bit 7 = 1 in the configuration register)
13-bit resolution (sign + 12-bit)
16-bit resolution (sign + 15-bit)
Continuous conversion and one-shot conversion mode
First conversion on power-up only
Conversion time for 1 SPS mode
Temperature cycle = 25°C to 125°C, and back to 25°C
TA = 25°C
TA = 25°C
CT and INT pins pulled up to 5.5 V
VOH = 5 .5V
IOL = 2 mA @ 5.5 V, IOL = 1 mA @ 3.3 V
VIN = 0 V to VDD
ISOURCE = ISINK = 200 μA
IOL = 200 μA
Peak current while converting, SPI interface inactive
Peak current while converting, SPI interface inactive
VDD = 3.3 V, 1 SPS mode, TA = 25°C
VDD = 5.5 V, 1 SPS mode, TA = 25°C
Supply current in shutdown mode
Supply current in shutdown mode
VDD = 3.3 V, normal mode at 25°C
Power dissipated for VDD = 3.3 V, TA = 25°C
1 Accuracy includes lifetime drift.
Rev. 0 | Page 3 of 24



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SPI TIMING SPECIFICATIONS
TA = −55°C to +150°C, VDD = 2.7 V to 5.5 V, unless otherwise noted. All input signals are specified with rise time (tR) = fall time (tF) = 5 ns
(10% to 90% of VDD) and timed from a voltage level of 1.6 V.
Table 2.
Parameter1, 2
t1
t2
t3
t4
t5
t6
t7 4
t8
t9
t10
Limit at TMIN, TMAX (B Version)
0
100
100
30
25
0
60
80
10
80
0
0
60
80
10
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns min
ns min
ns max
ns max
ns min
Conditions/Comments
CS falling edge to SCLK active edge setup time3
SCLK high pulse width
SCLK low pulse width
Data valid to SCLK edge setup time
Data valid to SCLK edge hold time
SCLK active edge to data valid delay3
VDD = 4.5 V to 5.5 V
VDD = 2.7 V to 3.6 V
Bus relinquish time after CS inactive edge
CS rising edge to SCLK edge hold time
CS falling edge to DOUT active time
VDD = 4.5 V to 5.5 V
VDD = 2.7 V to 3.6 V
SCLK inactive edge to DOUT high
1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
2 See Figure 2.
3 SCLK active edge is falling edge of SCLK.
4 This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and, as such, are independent of external bus loading
capacitances.
CS
SCLK
DIN
DOUT
t1 t2
1
t4
t5
MSB
t9
t3
23
7812
LSB
t6
MSB
Figure 2. Detailed SPI Timing Diagram
t8
78
t10
t7
LSB
ISINK (1.6mA WITH VDD = 5V,
100µA WITH VDD = 3V)
TO
OUTPUT
PIN
10pF
1.6V
ISOURCE (200µA WITH VDD = 5V,
100µA WITH VDD = 3V)
Figure 3. Load Circuit for Timing Characterization
Rev. 0 | Page 4 of 24






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