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J112 (ON Semiconductor) : Total 5 Pages

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J111, J112
JFET Chopper Transistors
N−Channel — Depletion
Features
Pb−Free Packages are Available*
MAXIMUM RATINGS
Rating
Symbol Value
Unit
Drain −Gate Voltage
Gate −Source Voltage
Gate Current
Total Device Dissipation @ TA = 25°C
Derate above = 25°C
VDG
VGS
IG
PD
−35 Vdc
−35 Vdc
50 mAdc
350 mW
2.8 mW/°C
Lead Temperature
Operating and Storage Junction
Temperature Range
TL 300
TJ, Tstg −65 to +150
°C
°C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
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1 DRAIN
3
GATE
2 SOURCE
TO−92
CASE 29−11
1
2
STYLE 5
3
MARKING DIAGRAM
J11x
AYWW G
G
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
March, 2006 − Rev. 2
1
J11x = Device Code
x = 1 or 2
A = Assembly Location
Y = Year
WW = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
Publication Order Number:
J111/D



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J111, J112
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Characteristic
OFF CHARACTERISTICS
Gate −Source Breakdown Voltage
(IG = −1.0 mAdc)
Gate Reverse Current
(VGS = −15 Vdc)
Gate Source Cutoff Voltage
(VDS = 5.0 Vdc, ID = 1.0 mAdc)
J111
J112
Drain−Cutoff Current
(VDS = 5.0 Vdc, VGS = −10 Vdc)
ON CHARACTERISTICS
Zero−Gate−Voltage Drain Current(1)
(VDS = 15 Vdc)
J111
J112
Symbol
V(BR)GSS
IGSS
VGS(off)
ID(off)
IDSS
Static Drain−Source On Resistance
(VDS = 0.1 Vdc)
Drain Gate and Source Gate On−Capacitance
(VDS = VGS = 0, f = 1.0 MHz)
Drain Gate Off−Capacitance
(VGS = −10 Vdc, f = 1.0 MHz)
Source Gate Off−Capacitance
(VGS = −10 Vdc, f = 1.0 MHz)
1. Pulse Width = 300 ms, Duty Cycle = 3.0%.
J111
J112
rDS(on)
Cdg(on)
+
Csg(on)
Cdg(off)
Csg(off)
Min
35
− 3.0
− 1.0
20
5.0
2.0
Max
− 1.0
− 10
− 5.0
1.0
30
50
28
5.0
5.0
Unit
Vdc
nAdc
Vdc
nAdc
mAdc
W
pF
pF
pF
ORDERING INFORMATION
Device
Package
Shipping
J111RL1
J111RL1G
TO−92
TO−92
(Pb−Free)
2000 Units / Tape & Reel
J111RLRA
J111RLRAG
TO−92
TO−92
(Pb−Free)
2000 Units / Tape & Reel
J111RLRP
J111RLRPG
TO−92
TO−92
(Pb−Free)
2000 Units / Tape & Reel
J112
J112G
TO−92
TO−92
(Pb−Free)
1000 Units / Bulk
J112RL1
J112RL1G
TO−92
TO−92
(Pb−Free)
2000 Units / Tape & Reel
J112RLRA
J112RLRAG
TO−92
TO−92
(Pb−Free)
2000 Units / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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2



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J111, J112
TYPICAL SWITCHING CHARACTERISTICS
1000
500
200 RK = RD
100
50
TJ = 25°C
J111 VGS(off) = 12 V
J112 = 7.0 V
J113 = 5.0 V
1000
500
200
100
50
RK = RD
TJ = 25°C
J111 VGS(off) = 12 V
J112 = 7.0 V
J113 = 5.0 V
20
10
5.0 RK = 0
20
10 RK = 0
5.0
2.0
1.0
0.5 0.7 1.0
2.0 3.0 5.0 7.0 10
ID, DRAIN CURRENT (mA)
20 30
Figure 1. Turn−On Delay Time
50
2.0
1.0
0.5 0.7 1.0
2.0 3.0 5.0 7.0 10
ID, DRAIN CURRENT (mA)
Figure 2. Rise Time
20 30
50
1000
500 TJ = 25°C
J111 VGS(off) = 12 V
200 J112 = 7.0 V
100 J113 = 5.0 V
50 RK = RD
20
10
5.0 RK = 0
2.0
1.0
0.5 0.7 1.0
2.0 3.0 5.0 7.0 10
ID, DRAIN CURRENT (mA)
20 30
Figure 3. Turn−Off Delay Time
50
1000
500
RK = RD
TJ = 25°C
J111 VGS(off) = 12 V
200 J112 = 7.0 V
100 J113 = 5.0 V
50
20 RK = 0
10
5.0
2.0
1.0
0.5 0.7 1.0
2.0 3.0 5.0 7.0 10
ID, DRAIN CURRENT (mA)
Figure 4. Fall Time
20 30 50
RGEN
50 W
VGEN
+VDD
INPUT
SET VDS(off) = 10 V
RK
RD
RT
50 W
RGG
VGG
50 W
INPUT PULSE
tr 0.25 ns
tf 0.5 ns
PULSE WIDTH = 2.0 ms
DUTY CYCLE 2.0%
RGG & RK
RDȀ
+
RD(RT ) 50)
RD ) RT ) 50
Figure 5. Switching Time Test Circuit
OUTPUT
NOTE 1
The switching characteristics shown above were measured using a test
circuit similar to Figure 5. At the beginning of the switching interval,
the gate voltage is at Gate Supply Voltage (−VGG). The Drain−Source
Voltage (VDS) is slightly lower than Drain Supply Voltage (VDD) due
to the voltage divider. Thus Reverse Transfer Capacitance (Crss) or
Gate−Drain Capacitance (Cgd) is charged to VGG + VDS.
During the turn−on interval, Gate−Source Capacitance (Cgs)
discharges through the series combination of RGen and RK. Cgd must
discharge to VDS(on) through RG and RK in series with the parallel
combination of effective load impedance (RD) and Drain−Source
Resistance (rds). During the turn−off, this charge flow is reversed.
Predicting turn−on time is somewhat difficult as the channel resistance
rds is a function of the gate−source voltage. While Cgs discharges, VGS
approaches zero and rds decreases. Since Cgd discharges through rds,
turn−on time is non−linear. During turn−off, the situation is reversed
with rds increasing as Cgd charges.
The above switching curves show two impedance conditions; 1) RK
is equal to RD, which simulates the switching behavior of cascaded
stages where the driving source impedance is normally the load
impedance of the previous stage, and 2) RK = 0 (low impedance) the
driving source impedance is that of the generator.
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J111, J112
20
J112
10 J113
7.0
J111
5.0 Tchannel = 25°C
VDS = 15 V
3.0
2.0
0.5 0.7 1.0
2.0 3.0 5.0 7.0 10
ID, DRAIN CURRENT (mA)
20 30 50
Figure 6. Typical Forward Transfer Admittance
15
10
Cgs
7.0
5.0 Cgd
3.0 Tchannel = 25°C
2.0 (Cds IS NEGLIGIBLE)
1.5
1.0
0.03 0.05 0.1
0.3 0.5 1.0
3.0 5.0
VR, REVERSE VOLTAGE (VOLTS)
10
Figure 7. Typical Capacitance
30
200
IDSS 25 50 mA 75 mA 100 mA
= 10 mA
160 mA
125 mA
120
80
40 Tchannel = 25°C
0
0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0
VGS, GATE−SOURCE VOLTAGE (VOLTS)
Figure 8. Effect of Gate−Source Voltage
On Drain−Source Resistance
2.0
1.8
ID = 1.0 mA
VGS = 0
1.6
1.4
1.2
1.0
0.8
0.6
0.4
−70
−40 −10 20 50 80 110 140
Tchannel, CHANNEL TEMPERATURE (°C)
Figure 9. Effect of Temperature On
Drain−Source On−State Resistance
170
100 Tchannel = 25°C
90
10
9.0
80 8.0
70 rDS(on) @ VGS = 0
60
50
VGS(off)
7.0
6.0
5.0
40 4.0
30 3.0
20 2.0
10 1.0
00
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
IDSS, ZERO−GATE−VOLTAGE DRAIN CURRENT (mA)
Figure 10. Effect of IDSS On Drain−Source
Resistance and Gate−Source Voltage
NOTE 2
The Zero−Gate−Voltage Drain Current (IDSS), is the
principle determinant of other J-FET characteristics.
Figure 10 shows the relationship of Gate−Source Off
Voltage (VGS(off) and Drain−Source On Resistance
(rds(on)) to IDSS. Most of the devices will be within ±10%
of the values shown in Figure 10. This data will be useful
in predicting the characteristic variations for a given part
number.
For example:
Unknown
rds(on) and VGS range for an J112
The electrical characteristics table indicates that an J112
has an IDSS range of 25 to 75 mA. Figure 10, shows
rds(on) = 52 W for IDSS = 25 mA and 30 W for
IDSS = 75 mA. The corresponding VGS values are 2.2 V
and 4.8 V.
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