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ARM940T
(Rev 2)
Technical Reference Manual
Copyright © 1999, 2000 ARM Limited. All rights reserved.
ARM DDI 0144B



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ARM940T (Rev 2)
Technical Reference Manual
Copyright © 1999, 2000 ARM Limited. All rights reserved.
Release Information
Date
12th February 1999
22nd November 2000
Issue
A
B
Change
First release.
Second release.
Change history
Proprietary Notice
Words and logos marked with ® or are registered trademarks or trademarks owned by ARM Limited, except
as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the
trademarks of their respective owners.
Neither the whole nor any part of the information contained in, or the product described in, this document
may be adapted or reproduced in any material form except with the prior written permission of the copyright
holder.
The product described in this document is subject to continuous developments and improvements. All
particulars of the product and its use contained in this document are given by ARM in good faith. However,
all warranties implied or expressed, including but not limited to implied warranties of merchantability, or
fitness for purpose, are excluded.
This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable
for any loss or damage arising from the use of any information in this document, or any error or omission in
such information, or any incorrect use of the product.
Figure C-2 on page C-4 reprinted with permission IEEE Std 1149.1-1990, IEEE Standard Test Access Port
and Boundary-Scan Architecture Copyright 2000, by IEEE. The IEEE disclaims any responsibility or
liability resulting from the placement and use in the described manner.
Confidentiality Status
This document is Open Access. This document has no restriction on distribution.
Product Status
The information in this document is final (information on a developed product).
Web Address
http://www.arm.com
ii
Copyright © 1999, 2000 ARM Limited. All rights reserved.
ARM DDI 0144B



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Contents
ARM940T (Rev 2) Technical Reference Manual
Chapter 1
Chapter 2
Chapter 3
Preface
About this document .................................................................................... viii
Further reading ............................................................................................. xii
Feedback ..................................................................................................... xiii
Introduction
1.1 About the ARM940T ................................................................................... 1-2
1.2 Processor functional block diagram ............................................................ 1-3
Programmer’s Model
2.1 About the programmer’s model ................................................................... 2-2
2.2 About the ARM9TDMI programmer’s model ............................................... 2-3
2.3 CP15 register map summary ...................................................................... 2-5
Protection Unit
3.1 About the protection unit ............................................................................. 3-2
3.2 Enabling the protection unit ........................................................................ 3-3
3.3 Memory regions .......................................................................................... 3-4
3.4 Overlapping regions .................................................................................... 3-7
ARM DDI 0144B
Copyright © 1999, 2000 ARM Limited. All rights reserved.
iii



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Contents
Chapter 4
Chapter 5
Chapter 6
Chapter 7
Chapter 8
Caches and Write Buffer
4.1 Cache architecture ..................................................................................... 4-2
4.2 ICache ........................................................................................................ 4-5
4.3 DCache ....................................................................................................... 4-8
4.4 The write buffer ......................................................................................... 4-12
4.5 Cache lockdown ....................................................................................... 4-16
Clock Modes
5.1 About ARM940T clocking ........................................................................... 5-2
5.2 FastBus mode ............................................................................................ 5-3
5.3 Synchronous mode ..................................................................................... 5-4
5.4 Asynchronous mode ................................................................................... 5-6
Bus Interface Unit
6.1 About the ARM940T bus interface ............................................................. 6-2
6.2 ASB transfers ............................................................................................. 6-3
6.3 External aborts ......................................................................................... 6-17
6.4 Memory access order ............................................................................... 6-18
Coprocessor Interface
7.1 About the coprocessor interface ................................................................. 7-2
7.2 LDC or STC ................................................................................................ 7-5
7.3 MCR/MRC .................................................................................................. 7-9
7.4 Interlocked MCR ....................................................................................... 7-11
7.5 CDP .......................................................................................................... 7-13
7.6 Privileged instructions ............................................................................... 7-15
7.7 Busy-waiting and interrupts ...................................................................... 7-17
Debug Support
8.1 About debug support .................................................................................. 8-2
8.2 Debug systems ........................................................................................... 8-3
8.3 Debug interface signals .............................................................................. 8-5
8.4 Scan chains and JTAG interface .............................................................. 8-11
8.5 The JTAG state machine .......................................................................... 8-12
8.6 Test data registers .................................................................................... 8-18
8.7 ARM940T core clocks .............................................................................. 8-27
8.8 Determining the core and system state .................................................... 8-29
8.9 Exit from debug state ................................................................................ 8-33
8.10 The behavior of the program counter during debug ................................. 8-36
8.11 EmbeddedICE unit ................................................................................... 8-39
8.12 Vector catching ......................................................................................... 8-46
8.13 Single-stepping ......................................................................................... 8-47
8.14 Debug communications channel .............................................................. 8-48
8.15 The debugger view of the cache .............................................................. 8-52
iv
Copyright © 1999, 2000 ARM Limited. All rights reserved.
ARM DDI 0144B





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