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ARM946E-S
Revision: r1p1
Technical Reference Manual
Copyright © 2001-2003 ARM Limited. All rights reserved.
ARM DDI 0201C



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ARM946E-S
Technical Reference Manual
Copyright © 2001-2003 ARM Limited. All rights reserved.
Release Information
The following changes have been made to this document.
Change history
Date
Issue Change
16 February 2001 A
17 May 2002
B
15 May 2003
C
First release
Second release
Third release
Proprietary Notice
Words and logos marked with ® or are registered trademarks or trademarks of ARM Limited in the EU and
other countries, except as otherwise stated below in this proprietary notice. Other brands and names
mentioned herein may be the trademarks of their respective owners.
Neither the whole nor any part of the information contained in, or the product described in, this document
may be adapted or reproduced in any material form except with the prior written permission of the copyright
holder.
The product described in this document is subject to continuous developments and improvements. All
particulars of the product and its use contained in this document are given by ARM in good faith. However,
all warranties implied or expressed, including but not limited to implied warranties of merchantability, or
fitness for purpose, are excluded.
This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable
for any loss or damage arising from the use of any information in this document, or any error or omission in
such information, or any incorrect use of the product.
Confidentiality Status
This document is Open Access. This document has no restriction on distribution.
Product Status
The information in this document is final, that is for a developed product.
Web Address
http://www.arm.com
ii
Copyright © 2001-2003 ARM Limited. All rights reserved.
ARM DDI 0201C



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Contents
ARM946E-S Technical Reference Manual
Chapter 1
Chapter 2
Chapter 3
Chapter 4
ARM DDI 0201C
Preface
About this document .................................................................................... xiv
Feedback ..................................................................................................... xix
Introduction
1.1 About the ARM946E-S processor ............................................................... 1-2
1.2 ARM946E-S block diagram ......................................................................... 1-3
1.3 Differences between processor versions .................................................... 1-5
Programmer’s Model
2.1 About the ARM946E-S programmers model .............................................. 2-2
2.2 About the ARM9E-S programmers model .................................................. 2-3
2.3 CP15 register map summary ...................................................................... 2-4
Caches
3.1 About cache architecture ............................................................................ 3-2
3.2 Instruction cache ......................................................................................... 3-6
3.3 Data cache ................................................................................................. 3-8
3.4 Cache lockdown ........................................................................................ 3-12
Protection Unit
4.1 About the protection unit ............................................................................. 4-2
Copyright © 2001-2003 ARM Limited. All rights reserved.
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Contents
Chapter 5
Chapter 6
Chapter 7
Chapter 8
Chapter 9
4.2 Memory regions .......................................................................................... 4-3
4.3 Overlapping regions ................................................................................... 4-6
Tightly-Coupled Memory Interface
5.1 ARM946E-S TCM interface description ...................................................... 5-2
5.2 Using CP15 Control Register ..................................................................... 5-3
5.3 Enabling the Instruction TCM during soft reset .......................................... 5-7
5.4 Data TCM accesses ................................................................................... 5-8
5.5 Instruction TCM accesses .......................................................................... 5-9
Bus Interface Unit and Write Buffer
6.1 About the BIU and write buffer ................................................................... 6-2
6.2 AHB bus master interface ........................................................................... 6-3
6.3 Noncached Thumb instruction fetches ..................................................... 6-10
6.4 AHB clocking ............................................................................................ 6-11
6.5 The write buffer ......................................................................................... 6-14
Coprocessor Interface
7.1 About the coprocessor interface ................................................................. 7-2
7.2 Coprocessor interface signals .................................................................... 7-3
7.3 LDC/STC .................................................................................................. 7-11
7.4 MCR/MRC ................................................................................................ 7-13
7.5 Interlocked MCR ....................................................................................... 7-14
7.6 CDP .......................................................................................................... 7-15
7.7 Privileged instructions ............................................................................... 7-16
7.8 Busy-waiting and interrupts ...................................................................... 7-17
ETM Interface
8.1 About the ETM interface ............................................................................. 8-2
8.2 Enabling the ETM interface ........................................................................ 8-3
8.3 ARM946E-S trace support features ............................................................ 8-4
Debug Support
9.1 About the debug interface .......................................................................... 9-2
9.2 Debug systems ........................................................................................... 9-4
9.3 The JTAG state machine ............................................................................ 9-7
9.4 Scan chains .............................................................................................. 9-12
9.5 Debug access to the caches .................................................................... 9-18
9.6 Debug interface signals ............................................................................ 9-20
9.7 Determining the core and system state .................................................... 9-25
9.8 Overview of EmbeddedICE-RT ................................................................ 9-26
9.9 Disabling EmbeddedICE-RT .................................................................... 9-28
9.10 The debug communication channel .......................................................... 9-29
9.11 Monitor mode debugging .......................................................................... 9-33
iv
Copyright © 2001-2003 ARM Limited. All rights reserved.
ARM DDI 0201C





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