s Static CMOS Design with Low-Power Standby Mode
s 32-Bit Internal Data Paths and ALU
s Operating Frequency
- DC-to-18 MHz at 5V
- DC-to-10 MHz at 3.3V
s Enhanced Instruction Set that Maintains Object-Code
Compatibility with Z80® and Z180™ Microprocessors
s 16-Bit (64K) or 32-Bit (4G) Linear Address Space
s 16-Bit Data Bus with Dynamic Sizing
s Two-Clock Cycle Instruction Execution Minimum
s Four Banks of On-Chip Register Files
s Enhanced Interrupt Capabilities, Including
s Undefined Opcode Trap for Z380™ Instruction Set
s On-Chip I/O Functions:
- Six-Memory Chip Selects with Programmable Waits
- Programmable I/O Waits
- DRAM Refresh Controller
s 100-Pin QFP Package
The Z380™ Microprocessor is an integrated high-
performance microprocessor with fast andefficientthrough-
put and increased memory addressing capabilities. The
Z380™ offers a continuing growth path for present Z80-or
Z180-based designs, while maintaining Z80® CPU and
Z180® MPU object-code compatibility. The Z380™ MPU
enhancements include an improved 280 CPU, expanded
4-Gbyte space and flexible bus interface timing.
An enhanced version of the Z80 CPU is key to the Z380
MPU. The basic addressing modes of the Z80 micropro-
cessor have been augmented as follows: Stack Pointer
Relative loads and stores, 16-bit and 24-bit indexed off-
sets, and more flexible Indirect Register addressing, with
all of the addressing modes allowing access to the entire
32-bit address space. Additions made to the instruction
set, include a full complement of 16-bit arithmetic and
logical operations, 16-bit I/O operations, multiply and
divide, plus a complete set of register-to-register loads
The expanded basic register file of the Z80 MPU micropro-
cessor includes alternate register versions of the IX and IY
registers. There are four sets of this basic Z80 micropro-
cessor register file present in the Z380 MPU, along with the
necessary resources to manage switching between the
different register sets. All of the register-pairs and index
registers in the basic Z80 microprocessor register file are
expanded to 32 bits.
GENERAL DESCRIPTION (Continued)
The Z380 MPU expands the basic 64 Kbyte Z80 and Z180
address space to a full 4 Gbyte (32-bit) address space.
This address space is linear and completely accessible to
the user program. The I/O address space is similarly
expanded to a full 4 Gbyte (32-bit) range and 16-bit I/O,
and both simple and block move are added.
Some features that have traditionally been handled by
external peripheral devices have been incorporated in the
design of the Z380 microprocessor. The on-chip peripher-
als reduce system chip count and reduce interconnection
on the external bus. The Z380 MPU contains a refresh
controller for DRAMs that employs a /CAS-before-/RAS
refresh cycle at a programmable rate and burst size.
Six programmable memory-chip selects are available,
along with programmable wait-state generators for each
chip-select address range.
The Z380 MPU provides flexible bus interface timing, with
separate control signals and timing for memory and
I/O. The memory bus control signals provide timing refer-
ences suitable for direct interface to DRAM, static RAM,
EPROM, or ROM. Full control of the memory bus timing is
possible because the /WAIT signal is sampled three times
during a memory transaction, allowing complete user
control of edge-to-edge timing between the reference
signals provided by the Z380 MPU. The I/O bus control
signals allow direct interface to members of the Z80 family
of peripherals, the Z8000 family of peripherals, or the
Z8500 series of peripherals. Figure 1 shows the Z380
block diagram; Figure 2 shows the pin assignments.
All signals with a preceding front slash, "/", are active Low
e.g., B//W (WORD is active Low); B/W is active Low, only)
Power connections follow conventional descriptions below:
External Interface Logic
www.DataSheet4U.com Figure 1. Z380 Functional Block Diagram
15 100-Pin QFP
30 35 40 45 50
Figure 2. 100-Pin QFP Pin Assignments
A31-A0 Address Bus (outputs, active High, tri-state). These
non-multiplexed address signals provide a linear memory
address space of four gigabytes. The 32-address signals
are also used to access I/O devices.
CLKsel Clock Option Select (input, active High). This
input should be connected to VDD to select the direct clock
option and should be connected to VSS for the crystal
/BACK Bus Acknowledge (output, active Low, tri-state).
This signal, when asserted, indicates that the Z380 MPU
has accepted an external bus request and has tri-stated its
output drivers for the address bus, data bus and the bus
control signals /TREFR, /TREFA, /TREFC, /BHEN, /BLEN,
/MRD, /MWR, /IORQ, /IORD, and /IOWR. Note that the
Z380 MPU cannot provide any DRAM refresh transactions
while it is in the bus acknowledge state.
/BHEN Byte High Enable (output, active Low, tri-state).
This signal is asserted at the beginning of a memory, or
refresh transaction to indicate that an operation on D15-D8
is requested. For a 16-bit memory transaction, if /MSIZE is
asserted, indicating a byte-wide memory, another memory
transaction is performed to transfer the data on D15-D8,
this time through D15-D8.
/BLEN Byte Low Enable (output, active Low, tri-state). This
signal is asserted at the beginning of a memory or refresh
transaction to indicate that an operation on D7-D0 is
requested. For a 16-bit memory transaction, if /MSIZE is
asserted, indicating a byte-wide memory, only the data on
D7-D0 will be transferred during this transaction, and
another transaction will be performed to transfer the data
on D15-D8, this time through D7-D0.
/BREQ Bus Request (input, active Low). When this signal
is asserted, an external bus master is requesting control of
the bus. /BREQ has higher priority than all nonmaskable
and maskable interrupt requests.
BUSCLK Bus Clock (output, active High, tri-state). This
signal, output by the Z380 MPU, is the reference edge for
the majority of other signals generated by the Z380 MPU.
BUSCLK is a delayed version of the CLK input.
D15-D0 Data Bus (input/outputs, active High, tri-state).
This bi-directional 16-bit data bus is used for data transfer
between the Z380 MPU and memory or I/O devices. Note
that for a memory word transfer, the even-addressed
(A0 = 0) byte is generally transferred on D15-D8, and the
odd-addressed (A0 = 1) byte on D7-D0 (see the /MSIZE
/EV Evaluation Mode (input, active Low). This input should
be left unconnected for normal operation. When it is driven
to logic 0, the Z380 MPU conditions itself in the reset mode
and tri-states all of its output pin drivers.
/HALT Halt Status (output, active Low, tri-state). If the Z380
MPU standby mode option is not selected, a Sleep instruc-
tion is executed no different than a Halt instruction, and the
one HALT signal goes active to indicate the CPU's HALT
state. If the standby mode option is selected, this signal
goes active only at the Halt instruction execution.
/STNBY Standby Status (output, active Low, tri-state). If
the Z380 MPU standby mode is selected, executing a
sleep instruction stops clocking within the Z380 MPU and
at BUSCLK and IOCLK after which this signal is asserted.
The Z380 MPU is then in the low power standby mode, with
all operations suspended.
/INT3-0 Interrupt Requests (inputs, active Low). These
signals are four asynchronous maskable interrupt inputs.
IOCLK I/O Clock (output, active High, tri-state). This signal
is a program controlled divided-down version of BUSCLK.
The division factor can be two, four, six or eight with I/O
transactions and interrupt-acknowledge transactions oc-
curring relative to IOCLK.
CLKI Clock/Crystal (input, active High). An externally
generated direct clock can be input at this pin and the
Z380 MPU would operate at the CLKI frequency. Alterna-
tively, a crystal up to 20 MHz can be connected across
CLKI and CLKO, and the Z380 MPU would operate at half
of the crystal frequency. The two clocking options are
controlled by the CLKsel input.
CLKO Crystal (output, active High). Crystal oscillator
connection. This pin should be left open if an externally
generated direct clock is input at the CLKI pin.
/INTAK Interrupt Acknowledge Status (output, active Low,
tri-state). This signal is used to distinguish between I/O and
interrupt acknowledge transactions. This signal is High
during I/O read and I/O write transactions and Low during
interrupt acknowledge transactions.
/IORQ Input/Output Request (output, active Low, tri-state).
This signal is active during all I/O read and write transac-
tions and interrupt acknowledge transactions.
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