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I.MX31 (Freescale Semiconductor) : Total 18 Pages

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Freescale Semiconductor
Product Brief
Document Number: MC1128MX31PB
Rev. 0.6, 06/2005
i.MX31 and i.MX31L
Multimedia Applications Processors
1 Introduction
The i.MX31 and i.MX31L multimedia applications
processors represent Freescale Semiconductor’s latest
achievement in multimedia integrated applications
processors that are part of a growing family of
multimedia-focused products offering high performance
processing optimized for lowest power consumption.
The i.MX31 and i.MX31L processors feature Freescale's
advanced and power-efficient implementation of the
ARM1136JF-S™ core, which operates at speeds starting
at 532 MHz.
Unless otherwise specified, the material in this product
brief is applicable to both the i.MX31 and i.MX31L
processors. Features include the following:
Smart Speed Technology—The heart of the
i.MX31 and i.MX31L processors is a level of
power management throughout the ICs that allow
the rich suite of multimedia features and
peripherals to achieve minimum system power
consumption in both active and various
low-power modes. Smart Speed Technology
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
© Freescale Semiconductor, Inc., 2005. All rights reserved.



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Features
enables the designer to deliver a feature-rich product that requires levels of power that are far less
than typical industry expectations.
Multimedia Powerhouse—The multimedia performances of the i.MX31 and i.MX31L processors
are each boosted by a multi-level cache system and further enhanced by an MPEG4 hardware
accelerator that provides MPEG4 SP encoding up to VGA resolution at 30 fps, as well as an
Autonomous Image Processing Unit, Vector Floating Point (VFP11) co-processor, and a
programmable DMA controller.
• Powerful Graphics Acceleration (not available in the i.MX31L)—3D graphics are the key to
mobile game designs. The i.MX31 processor delivers an integrated 3D Graphics Processing Unit
(GPU) that provides an incredible 0.8–0.9 MTri/sec (double textured, bi-linear, Gouraud shaded)
at about 100 Mpix/sec (effective).
Interface Flexibility—The i.MX31 and i.MX31L processors’ interface support connection to all
popular types of external memories—DDR, SDRAM, NAND Flash, NOR Flash, SRAM, and
MDOC. Designers seeking to provide products that deliver a rich multimedia experience will find
a full suite of on-chip peripherals: LCD controller and CMOS sensor interface, High Speed USB
On-The-Go, and two USB hosts, a multiple expansion card, and serial interfaces. There is even an
ATA hard disk controller in each processor. An important design goal of the i.MX31 and i.MX31L
processors is their rich and flexible connectivity support to ensure that any system configuration
can be developed quickly and at minimum material cost.
Increased Security—Because the need for advanced security for mobile devices continues to
increase, the i.MX31 and i.MX31L processors deliver hardware-enabled security features allowing
secure e-commerce, digital rights management (DRM), information encryption, secure boot, and
secure software downloads.
Regardless of whether you are designing a smart phone, PDA, gaming console, or other portable device,
the i.MX31 and i.MX31L processors provide your design with the power and flexibility necessary for
today’s competitive marketplace.
2 Features
Figure 1 on page 3 illustrates the functional modules of the i.MX31 and i.MX31L processors.
i.MX31 and i.MX31L Multimedia Applications Processors Product Brief, Rev. 0.6
2 Freescale Semiconductor



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Features
Connectivity
Internal
3 x CSPI
2 x SSI/I2S
3 x I2C
AUDMUX
External
5 x UART
USB OTG HS
2 x USB Host
1-Wire
Fast IrDA
Expansion
2 x MMC/SD
PCMCIA/CF
2 x Memory
Stick - Pro
SIM
ATA
CPU Complex
ARM1136TM CPU
Smart Speed
Switch (MAX)
I-Cache
D-Cache
L2-Cache
ROM
Patch
ETM
Vector Floating
Processor
Special
Functions
Security HW
Memory
Interface
SDRAM/DDR
NANDF Ctl
PSRAM
SmartMedia
Std System I/O
eDMA
3 x Timers
PWM
WD Timer
RTC
GPIO
RAM, ROM
System Control
JTAG, ETM
Bootstrap
System Reset
PLL &
Power Mgmt
Multimedia &
Human Interface
Graphics
Accelerator*
MPEG-4
Encoder
Keypad
Image
Processing Unit
Inversion and
Rotation
Camera I/F
Blending
Display/TV Ctl
Pre & Post
Processing
* Not available in i.MX31L
Figure 1. i.MX31 and i.MX31L Functional Block Diagram
2.1 ARM11™ Platform
The ARM11™ platform consists of the ARM1136JF-S processor, a level 2 (L2) cache system, 6 × 5
multi-layer AHB 2.v6 Smart Speed Crossbar Switch (MAX), L2 memory system, and an ARM11 vectored
interrupt controller (AVIC).
In addition, the ARM11 platform contains the Embedded Trace Kit™ (ETK) from ARM Ltd. These
modules consist of the Embedded Trace Macrocell™ (ETM™), the Embedded Trace Buffer™ (ETB™),
and the Cross Trigger Interface (CTI) module.
i.MX31 and i.MX31L Multimedia Applications Processors Product Brief, Rev. 0.6
Freescale Semiconductor
3



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Features
2.1.1 ARM1136JF-S Platform Modules
The modules that are used in the ARM1136JF-S Platform include the following:
The ARM1136JF-S CPU core—Based on the ARM® v6 architecture. It supports the
ARM Thumb® instruction set, Jazelle® technology to enable direct execution of Java™ byte codes,
and a range of SIMD DSP instructions that operate on 16-bit or 8-bit data values in 32-bit registers.
The VFP11 coprocessor—An ARM enhanced IEEE® 754 numeric coprocessor that can be used
to support and enhance 3D graphics, gaming, high resolution audio, Java, and other
general-purpose applications.
A Multi-Level Cache system—Consisting of a powerful L2 Cache Controller, 128 Kbytes unified
L2 cache memory and L2 cache monitor. The L2 cache controller (L2CC) module has been
optimized by ARM to Freescale’s specifications. The L1 cache provides 16 Kbytes for instruction
and 16 Kbytes for data.
Multi-Layer 6 × 5 AHB Smart Speed Crossbar Switch (MAX)—The L2CC master ports, the
off-platform alternate bus masters, and the ARM11 processor’s peripheral AHB arbitrate for
memory and peripherals via a 6 × 5 Multi-Layer AHB crossbar switch. The design of the MAX
allows concurrent transactions to proceed from any slave port to any master port. That is, it is
possible for five MAX slave ports to be active at the same time as a result of five independent
master requests.
If a particular slave port is simultaneously requested by more than one master port, arbitration logic
exists in the MAX to allow the higher priority master port to be granted access to the slave, while
stalling the other requestor(s) until that transaction is complete. The slave port arbitration schemes
supported are fixed, programmable fixed, round-robin, and programmable default parking.
L2 Memory System—The embedded 16 Kbytes SRAM and 32 Kbytes ROM are accessible by the
ARM CPU and the Enhanced DMA (eDMA) controller. ROM holds the High Assurance Boot
code.
2.2 Smart Power Management by Design
The i.MX31 and i.MX31L processors’ power management system includes an effective combination of
established and ground-breaking (patent pending) technologies to ensure the following design goals are
achieved:
• The operation of the IC is well balanced, providing the optimum trade-off between performance
and power consumption.
• Power is expended only when it is actually required by an application.
• When power is required, the minimum amount of power is used to complete the application.
There is always a trade-off between the potential performance that can be achieved and the leakage current
that is unavoidable to obtain a high level of performance because higher performance requires solid state
devices with increased leakage. To ensure the best possible performance trade-off, the i.MX31 and
i.MX31L processors are manufactured using a 90-nm, low-power process to ensure minimum power
dissipation by leakage. At the same time, dual Vt technology is used to incorporate the high performance
transistors in places where the performance is critical, therefore, producing the best overall trade-off
between performance and leakage.
i.MX31 and i.MX31L Multimedia Applications Processors Product Brief, Rev. 0.6
4 Freescale Semiconductor






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