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J112 (ON Semiconductor) : Total 4 Pages

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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
JFET Chopper Transistor
N–Channel — Depletion
3
GATE
1 DRAIN
2 SOURCE
Order this document
by J112/D
J112
MAXIMUM RATINGS
Rating
Symbol
Value
Drain – Gate Voltage
Gate – Source Voltage
Gate Current
Total Device Dissipation @ TA = 25°C
Derate above 25°C
VDG
VGS
IG
PD
– 35
– 35
50
350
2.8
Lead Temperature
Operating and Storage Junction
Temperature Range
TL
TJ, Tstg
300
– 65 to +150
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Characteristic
OFF CHARACTERISTICS
Gate – Source Breakdown Voltage
(IG = –1.0 µAdc)
Gate Reverse Current
(VGS = –15 Vdc)
Gate Source Cutoff Voltage
(VDS = 5.0 Vdc, ID = 1.0 µAdc)
Drain–Cutoff Current
(VDS = 5.0 Vdc, VGS = –10 Vdc)
ON CHARACTERISTICS
Zero–Gate–Voltage Drain Current(1)
(VDS = 15 Vdc)
Static Drain–Source On Resistance
(VDS = 0.1 Vdc)
Drain Gate and Source Gate On–Capacitance
(VDS = VGS = 0, f = 1.0 MHz)
Drain Gate Off–Capacitance
(VGS = –10 Vdc, f = 1.0 MHz)
Source Gate Off–Capacitance
(VGS = –10 Vdc, f = 1.0 MHz)
1. Pulse Width = 300 µs, Duty Cycle = 3.0%.
Unit
Vdc
Vdc
mAdc
mW
mW/°C
°C
°C
Symbol
V(BR)GSS
IGSS
VGS(off)
ID(off)
IDSS
rDS(on)
Cdg(on)
+
Csg(on)
Cdg(off)
Csg(off)
1
23
CASE 29–04, STYLE 5
TO–92 (TO–226AA)
Min
35
– 1.0
Max
– 1.0
– 5.0
1.0
Unit
Vdc
nAdc
Vdc
nAdc
5.0 — mAdc
— 50
— 28
pF
— 5.0
— 5.0
pF
pF
(Replaces J111/D)
©MMotootorroollaa,
Small–Signal
Inc. 1997
Transistors,
FETs
and
Diodes
Device
Data
1



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J112
TYPICAL SWITCHING CHARACTERISTICS
1000
500
200
100 RK = RD
50
TJ = 25°C
VGS(off) = 7.0 V
20
10
5.0
RK = 0
2.0
1.0
0.5 0.7 1.0
2.0 3.0 5.0 7.0 10
ID, DRAIN CURRENT (mA)
20 30
Figure 1. Turn–On Delay Time
50
1000
500
200 RK = RD
100
50
TJ = 25°C
VGS(off) = 7.0 V
20
10
5.0 RK = 0
2.0
1.0
0.5 0.7 1.0
2.0 3.0 5.0 7.0 10
ID, DRAIN CURRENT (mA)
Figure 2. Rise Time
20 30
50
1000
500
TJ = 25°C
200 VGS(off) = 7.0 V
100
50 RK = RD
20
10 RK = 0
5.0
2.0
1.0
0.5 0.7 1.0
2.0 3.0 5.0 7.0 10
ID, DRAIN CURRENT (mA)
20 30
Figure 3. Turn–Off Delay Time
50
1000
500
200 RK = RD
100
50
20 RK = 0
10
5.0
TJ = 25°C
VGS(off) = 7.0 V
2.0
1.0
0.5 0.7 1.0
2.0 3.0 5.0 7.0 10
ID, DRAIN CURRENT (mA)
Figure 4. Fall Time
20 30 50
RGEN
50
VGEN
+VDD
SET VDS(off) = 10 V
INPUT RK
RD
RT
RGG
50
VGG
50
OUTPUT
INPUT PULSE
tr 0.25 ns
tf 0.5 ns
PULSE WIDTH = 2.0 µs
DUTY CYCLE 2.0%
&RGG RK
)RD(RT 50)
Ȁ + ) )RD RD RT 50
Figure 5. Switching Time Test Circuit
NOTE 1
The switching characteristics shown above were measured using a
test circuit similar to Figure 5. At the beginning of the switching
interval, the gate voltage is at Gate Supply Voltage (–VGG). The
Drain–Source Voltage (VDS) is slightly lower than Drain Supply
Voltage (VDD) due to the voltage divider. Thus Reverse Transfer
Capacitance (Crss) or Gate–Drain Capacitance (Cgd) is charged to
VGG + VDS.
During the turn–on interval, Gate–Source Capacitance (Cgs)
discharges through the series combination of RGen and RK. Cgd
must discharge to VDS(on) through RG and RK in series with the
parallel combination of effective load impedance (RD) and
Drain–Source Resistance (rds). During the turn–off, this charge flow
is reversed.
Predicting turn–on time is somewhat difficult as the channel
resistance rds is a function of the gate–source voltage. While Cgs
discharges, VGS approaches zero and rds decreases. Since Cgd
discharges through rds, turn–on time is non–linear. During turn–off,
the situation is reversed with rds increasing as Cgd charges.
The above switching curves show two impedance conditions;
1) RK is equal to RD, which simulates the switching behavior of
cascaded stages where the driving source impedance is normally
the load impedance of the previous stage, and 2) RK = 0 (low
impedance) the driving source impedance is that of the generator.
2 Motorola Small–Signal Transistors, FETs and Diodes Device Data



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20
10
7.0
5.0 Tchannel = 25°C
VDS = 15 V
3.0
2.0
0.5 0.7 1.0
2.0 3.0 5.0 7.0 10
ID, DRAIN CURRENT (mA)
20 30 50
Figure 6. Typical Forward Transfer Admittance
J112
15
10
Cgs
7.0
5.0 Cgd
3.0 Tchannel = 25°C
2.0 (Cds IS NEGLIGIBLE)
1.5
1.0
0.03 0.05 0.1
0.3 0.5 1.0
3.0 5.0
VR, REVERSE VOLTAGE (VOLTS)
10
Figure 7. Typical Capacitance
30
200
IDSS 25 50 mA 75 mA 100 mA
= 10 mA
160 mA
125 mA
120
80
40 Tchannel = 25°C
0
0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0
VGS, GATE–SOURCE VOLTAGE (VOLTS)
Figure 8. Effect of Gate–Source Voltage
On Drain–Source Resistance
2.0
1.8
ID = 1.0 mA
VGS = 0
1.6
1.4
1.2
1.0
0.8
0.6
0.4
– 70
– 40 – 10 20 50 80 110 140
Tchannel, CHANNEL TEMPERATURE (°C)
Figure 9. Effect of Temperature On
Drain–Source On–State Resistance
170
100 Tchannel = 25°C
90
10
9.0
80 8.0
70 rDS(on) @ VGS = 0
60
50
VGS(off)
7.0
6.0
5.0
40 4.0
30 3.0
20 2.0
10 1.0
00
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
IDSS, ZERO–GATE–VOLTAGE DRAIN CURRENT (mA)
Figure 10. Effect of IDSS On Drain–Source
Resistance and Gate–Source Voltage
NOTE 2
The Zero–Gate–Voltage Drain Current (IDSS), is the principle
determinant of other J-FET characteristics. Figure 10 shows
the relationship of Gate–Source Off Voltage (VGS(off) and
Drain–Source On Resistance (rds(on)) to IDSS. Most of the
devices will be within ±10% of the values shown in Figure 10.
This data will be useful in predicting the characteristic
variations for a given part number.
For example:
Unknown
rds(on) and VGS range for an J112
The electrical characteristics table indicates that an J112
has an IDSS range of 25 to 75 mA. Figure 10, shows rds(on) =
52 Ohms for IDSS = 25 mA and 30 Ohms for IDSS = 75 mA.
The corresponding VGS values are 2.2 volts and 4.8 volts.
Motorola Small–Signal Transistors, FETs and Diodes Device Data
3



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J112
PACKAGE DIMENSIONS
R
SEATING
PLANE
AB
P
L
F
K
XX
H
V
G
C
1
N
N
D
J
SECTION X–X
CASE 029–04
(TO–226AA)
ISSUE AD
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. CONTOUR OF PACKAGE BEYOND DIMENSION R
IS UNCONTROLLED.
4. DIMENSION F APPLIES BETWEEN P AND L.
DIMENSION D AND J APPLY BETWEEN L AND K
MINIMUM. LEAD DIMENSION IS UNCONTROLLED
IN P AND BEYOND DIMENSION K MINIMUM.
INCHES
DIM MIN MAX
A 0.175 0.205
B 0.170 0.210
C 0.125 0.165
D 0.016 0.022
F 0.016 0.019
G 0.045 0.055
H 0.095 0.105
J 0.015 0.020
K 0.500 –––
L 0.250 –––
N 0.080 0.105
P ––– 0.100
R 0.115 –––
V 0.135 –––
MILLIMETERS
MIN MAX
4.45 5.20
4.32 5.33
3.18 4.19
0.41 0.55
0.41 0.48
1.15 1.39
2.42 2.66
0.39 0.50
12.70 –––
6.35 –––
2.04 2.66
––– 2.54
2.93 –––
3.43 –––
STYLE 5:
PIN 1.
2.
3.
DRAIN
SOURCE
GATE
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
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4 Motorola Small–Signal Transistors, FETs and Diodes Device DJa11ta2/D






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