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4.80E+31 (Holtek Semiconductor Inc) : Total 44 Pages

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Preliminary
HT48E30
8-Bit I/O Type MCU (With EEPROM)
Features
· Operating voltage:
fSYS=4MHz: 2.2V~5.5V
fSYS=8MHz: 3.3V~5.5V
· Low voltage reset function
· 23 bidirectional I/O lines (max.)
· 1 interrupt input shared with an I/O line
· 8-bit programmable timer/event counter with overflow
interrupt and 8-stage prescaler
· On-chip crystal and RC oscillator
· Watchdog Timer
· 2048´14 program memory ROM (MTP)
· 128´8 data memory EEPROM
· 96´8 data memory RAM
· Buzzer driving pair and PFD supported
General Description
The HT48E30 is an 8-bit high performance, RISC archi-
tecture microcontroller device specifically designed for
multiple I/O control product applications.
The advantages of low power consumption, I/O flexibil-
ity, timer functions, oscillator options, HALT and
· HALT function and wake-up feature reduce power
consumption
· 4-level subroutine nesting
· Up to 0.5ms instruction cycle with 8MHz system clock
at VDD=5V
· Bit manipulation instruction
· 14-bit table read instruction
· 63 powerful instructions
· 106 erase/write cycles EEPROM data memory
· EEPROM data retention > 10 years
· All instructions in one or two machine cycles
· In system programming (ISP)
· 24/28-pin SKDIP/SOP package
wake-up functions, watchdog timer, buzzer driver, as
well as low cost, enhance the versatility of these devices
to suit a wide range of application possibilities such as
industrial control, consumer products, subsystem con-
trollers, etc.
Block Diagram
IN T /P G 0
P ro g ra m
ROM
In s tr u c tio n
R e g is te r
P ro g ra m
C o u n te r
STAC K
4 L e v e ls
In te rru p t
C ir c u it
IN T C
PG 0
MP M
U
X
D ATA
M e m o ry
In s tr u c tio n
D ecoder
T im in g
G e n e ra to r
O SC2
O SC1
RES
VDD
VSS
M UX
A LU
S h ifte r
STATU S
PG 1
PG 2
ACC
D a ta M e m o ry
EEPRO M
EECR
TM R 0
TM R 0C
M fS Y S
M
P r e s c a le r
U
UX
X T M R /P C 0
W D TS
W D T P r e s c a le r
E N /D IS
W DT
fS Y S /4
M
U
X
W DT O SC
PAC PO RT A
PA
B Z /B Z
PBC PO RT B
PB
P A 0~P A 7
P B 0~P B 7
PCC PO RT C
PC
P C 0~P C 5
PG C PO RT G
PG
PG 0
Rev. 0.00
1 January 12, 2004



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Preliminary
HT48E30
Pin Assignment
PB5
PB4
PA3
PA2
PA1
PA0
PB3
PB2
P B 1 /B Z
P B 0 /B Z
VSS
P G 0 /IN T
1
2
3
4
5
6
7
8
9
10
11
12
24 P B 6
23 P B 7
22 P A 4
21 P A 5
20 P A 6
19 P A 7
18 O S C 2
17 O S C 1
16 V D D
15 R E S
14 P C 2
1 3 P C 0 /T M R
H T48E 30
2 4 S K D IP -A /S O P -A
Pad Assignment
PB5
PB4
PA3
PA2
PA1
PA0
PB3
PB2
P B 1 /B Z
P B 0 /B Z
VSS
P G 0 /IN T
P C 0 /T M R
PC1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 P B 6
27 P B 7
26 P A 4
25 P A 5
24 P A 6
23 P A 7
22 O S C 2
21 O S C 1
20 V D D
19 R E S
18 P C 5
17 P C 4
16 P C 3
15 P C 2
H T48E 30
2 8 S K D IP -A /S O P -A
T R IM 1
T R IM 2
T R IM 3
1 31 30 29 28 27 26 25
2
3
4
PA1
PA0
PB3
PB2
P B 1 /B Z
P B 0 /B Z
VSS
5
6
7
8
9
10
11
12 13 14 15 16 17
(0 ,0 )
24 P A 6
23 P A 7
22 O S C 2
21 O S C 1
20 V D D
19 R E S
18 P C 5
Rev. 0.00
* The IC substrate should be connected to VSS in the PCB layout artwork.
2 January 12, 2004



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Preliminary
HT48E30
Pad Description
Pad Name I/O
Options
Description
PA0~PA7
Pull-high*
Bidirectional 8-bit input/output port. Each bit can be configured as a
I/O
Wake-up
CMOS/Schmitt trigger
wake-up input by options. Software instructions determine the CMOS
output or Schmitt trigger or CMOS input (depends on options) with
Input
pull-high resistor (determined by 1-bit pull-high options).
PB0/BZ
PB1/BZ
PB2~PB7
I/O
Pull-high*
PB0 or BZ
PB1 or BZ
Bidirectional 8-bit input/output port. Software instructions determine the
CMOS output or Schmitt trigger input with pull-high resistor (deter-
mined by pull-high options).
The PB0 and PB1 are pin-shared with the BZ and BZ, respectively.
Once the PB0 or PB1 is selected as buzzer driving outputs, the output
signals come from an internal PFD generator (shared with timer/event
counter).
VSS
¾
¾ Negative power supply, ground
PG0/INT I/O
Pull-high*
Bidirectional I/O lines. Software instructions determine the CMOS out-
put or Schmitt trigger input with pull-high resistor (determined by 1-bit
pull-high options). This external interrupt input is pin-shared with PG0.
The external interrupt input is activated on a high to low transition.
PC0/TMR
PC1~PC5
I/O
Pull-high*
Bidirectional I/O lines. Software instructions determine the CMOS out-
put or Schmitt trigger input with pull-high resistor (determined by 1-bit
pull-high options). The timer input are pin-shared with PC0.
RES
I
¾ Schmitt trigger reset input. Active low.
VDD
¾
¾ Positive power supply
OSC1
OSC2
I
O
Crystal or RC
OSC1and OSC2 are connected to an RC network or Crystal (deter-
mined by options) for the internal system clock. In the case of RC oper-
ation, OSC2 is the output terminal for 1/4 system clock.
Note: ²*² The pull-high resistors of each I/O port (PA, PB, PC, PG) are controlled by a 1-bit option.
CMOS or Schmitt trigger option of port A is controlled by a 1-bit option.
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V
Input Voltage..............................VSS-0.3V to VDD+0.3V
Storage Temperature ............................-50°C to 125°C
Operating Temperature...........................-40°C to 85°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-
ity.
Rev. 0.00
3 January 12, 2004



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Preliminary
HT48E30
D.C. Characteristics
Symbol
Parameter
VDD Operating Voltage
IDD1 Operating Current (Crystal OSC)
IDD2 Operating Current (RC OSC)
IDD3 Operating Current (Crystal OSC)
ISTB1 Standby Current (WDT Enabled)
ISTB2
VIL1
VIH1
VIL2
VIH2
VLVR
IOL
Standby Current (WDT Disabled)
Input Low Voltage for I/O Ports
Input High Voltage for I/O Ports
Input Low Voltage (RES)
Input High Voltage (RES)
Low Voltage Reset Voltage
I/O Port Sink Current
IOH I/O Port Source Current
RPH Pull-high Resistance
Ta=25°C
Test Conditions
VDD Conditions
Min.
¾ fSYS=4MHz
2.2
¾ fSYS=8MHz
3.3
3V
No load, fSYS=4MHz
5V
¾
¾
3V
No load, fSYS=4MHz
5V
¾
¾
5V No load, fSYS=8MHz ¾
3V
No load, system HALT
5V
¾
¾
Typ.
¾
¾
0.6
2
0.8
2.5
3
¾
¾
Max.
5.5
5.5
1.5
4
1.5
4
5
5
10
Unit
V
V
mA
mA
mA
mA
mA
mA
mA
3V ¾ ¾ 1 mA
No load, system HALT
5V ¾ ¾ 2 mA
¾¾
0 ¾ 0.3VDD V
¾
¾
0.7VDD ¾
VDD
V
¾¾
0 ¾ 0.4VDD V
¾
¾
0.9VDD ¾
VDD
V
¾ LVR enabled
2.7 3.0 3.3
V
3V VOL=0.1VDD
4 8 ¾ mA
5V VOL=0.1VDD
10 20 ¾ mA
3V VOH=0.9VDD
-2 -4 ¾ mA
5V VOH=0.9VDD
-5 -10 ¾ mA
3V ¾
40 60 80 kW
5V ¾
10 30 50 kW
Rev. 0.00
4 January 12, 2004






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