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M-993 (Clare Inc.) : Total 6 Pages

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Features
Generates standard CCITT R1 MF tones
Digital input control
Linear (analog) output
Power output capable of driving standard line
14-pin DIP
Single 5-Volt supply
Inexpensive 3.58 MHz time base
Applications
Telephone systems
Test equipment
M-993
Region 1 MF Tone Generator
Description
The M-993 is a monolithic CMOS integrated circuit
designed to generate multifrequency (MF) tone pairs
for use in trunk signaling. The tones generated con-
form to CCITT R1 signal recommendations and to
AT&T MF standards. The M-993 permits design engi-
neers to implement a highly accurate MF sender with
a minimum of space, power, and added components.
The accuracy of the tone frequencies is assured
through use of an easily obtained 3.58 MHz color burst
crystal or an external 3.58 MHz clock source.
Ordering Information
Part #
M-993
Description
14-pin plastic DIP
Pin Diagram
Block Diagram
DS-M993-R1
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M-993
Absolute Maximum Ratings
Storage Temperature
-55 to 125°C
Operating Ambient Temperature
-25 to 70°C
VDD 7.0V
Any Input Voltage
VSS - 0.6 to VDD + 0.6V
Note:
1. Exceeding these ratings may permanently damage the M-993.
Absolute Maximum Ratings are stress ratings. Stresses in
excess of these ratings can cause permanent damage to
the device. Functional operation of the device at these or
any other conditions beyond those indicated in the opera-
tional sections of this data sheet is not implied. Exposure of
the device to the absolute maximum ratings for an extend-
ed period may degrade the device and effect its reliability.
Specifications
Parameter
Power Supply
and Reference
VDD
Current Drain, IDD
VREF PIN:
Voltage
Oscillator
Internal Resistance from VREF to VDD, VSS
Frequency Deviation
External CLock: (XOUT open)
VIL
VIH
Duty Cycle
XIN, XOUT Loading:
Capacitance
Resistance
Tone Output
Frequency Deviation
Level
Distorting Components
Idle
OUTDRIVE Envelope Rise Time
Control
DX, CE Pins:
VIL
VIH
Mute Pins:
VOL (ISINK = -100 µA)
VOH (ISOURCE = 100 µA)
Timing
Data Setup (tDSRT)
Data Hold (tDH)
Chip Enable Fall (tPL)
Tone On Delay (tTO)
Tone Off Delay (tTD)
Mute Delay from Outdrive (tMO)
Unless otherwise noted, VDD - VSS = 5 VDC, Ta - 25° C
Notes:
1. All DC voltages are referenced to VSS.
2. Vrms per tone, 540W load.
3. Any one frequency relative to the lowest level output tone (f<4000 Hz).
4. 0 dBm = 0.775 Vrms.
5. To 90% maximum amplitude.
Min
4.75
-
48% of VDD
3.25
-0.01
Typ Max Units
- 5.25 V
2.0/4.0
-
mA
-
52% of VDD
%
- 6.75 k
-
+0.01
%
Notes
1
8
-
-
7
0
VDD- 0.2
40
-
-
-
0.2 V -
VDD V -
60 % -
- - 10 pF 9
20 - - M-
-1.5 - 1.5 % -
110 - 180 mV 2
-35 - - dB 2, 3
- - -60 dBm 4
- - 4 ms 5
- - 0.5 V 6
2.5 - - V -
-
VDD- 1.5
200
10
-
5
5
-
-
-
-
-
-
-
-
-
1.5 V -
- V-
- ns 10
- ns -
90 ns -
- ms -
- ms -
200 ns -
6. For all supply voltages in the operating range.
7. At XOUT pin as compared to 3.579545 MHz.
8. OUTDRIVE with load >5 KW/OUTDRIVE with 540W load.
9. Crystal oscillator active.
10. Measured 90% to 10%.
2
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Pin Function
Pin
CE
D0 - D3
D4-D5
MUTE
OUTDRIVE
VDD
VREF
VSS
XIN
XOUT
Function
Latches data and enables output (active low
input).
Data input pins. (See Data/Tone Selection.)
Leave open.
Output indicates that a signal is being
generated at OUTDRIVE.
Linear buffered tone output.
Most positive power supply input pin.
Internally generated mid-power supply
voltage (output).
Most negative power supply input pin.
Crystal oscillator or digital clock input.
Crystal oscillator output.
Power-On Reset Circuit
M-993
Data/Tone Selection
D3 D2 D1 D0 Frequency (Hz)
12
0 0 0 0 1100
1700
0 0 0 1 700
900
0 0 1 0 700
1100
0 0 1 1 900
1100
0 1 0 0 700
1300
0 1 0 1 900
1300
0 1 1 0 1100
1300
0 1 1 1 700
1500
1 0 0 0 900
1500
1 0 0 1 1100
1500
1 0 1 0 1300
1500
1 0 1 1 1500
1700
1 1 0 0 900
1700
1 1 0 1 1300
1700
1 1 1 0 700
1700
Use
Key Pulse (KP)
Digit 1
Digit 2
Digit 3
Digit 4
Digit 5
Digit 6
Digit 7
Digit 8
Digit 9
Digit 0
ST
ST1
ST2
ST3
A typical control sequence for the M-993 is: (1) set
data lines Selection for data settings for a particular
tone pair output).to desired frequency selection, (2)
wait for data lines to settle, (3) drive the chip enable
(CE) low, (4) maintain CE low for desired tone duration
(Note: data lines may be changed after data hold
time), and (5) return CE to a logic high.
In a bus-oriented system, noise on the data lines may
propagate through the device and appear at the out-
put. To safeguard against this, use an external latch to
clock the data into the device. In addition, it is good
practice to bypass the VREF pin to ground with a small
capacitor (~0.01mF) to reduce power supply noise.
The designer should be aware of device timing
requirements and design accordingly. Beware of hard-
wiring the data input pins for dedicated tone genera-
tion. An RC network like that shown in Power-On
Reset Circuit should be used to momentarily reset the
device immediately following a power-up to ensure
reliable operation.
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M-993
Timing Diagram
Expanded Timing Diagram
Typical Application
4
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Rev. 1






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