• Generates standard call progress tones
• Digital input control
• Linear (analog) output
• Power output capable of driving standard line
• 14-pin DIP and 16-pin SOIC package types
• Single supply 5V CMOS (low power)
• Inexpensive 3.58 MHz time base
• Temperature range from -25ºC to 70ºC (-01 ver-
• Temperature range from -40ºC to 85ºC (-02 ver-
• Telephone systems
• Test equipment
• Security systems
• Billing systems
Call Progress Tone Generator
The M-991 is a call progress tone generator integrated
circuit for use in telephone systems. The circuit uses
low-power CMOS techniques to generate tones which
are digitally controlled and highly linear. The M-991 is
designed to permit operation with almost any system.
The use of integrated circuit techniques allows the M-
991 to incorporate the control, tone generating, and
power output buffer into a single 14-pin DIP or a 16-pin
SOIC. A 3.58-MHz (color burst) crystal-controlled time
base guarantees accuracy and repeatability.
14-pin plastic DIP
16-pin SOIC Tape and Reel
16-pin SOIC, Extended
16-pin SOIC, Extended
Temperature Range, Tape and
Absolute Maximum Ratings
-55° to 125° C
Operating Ambient Temperature
-25° to 70° C
Operating Ambient Temperature
for the M-991-02SM
-40° to 85° C
Any Input Voltage
VSS -0.6 to VDD +0.6V
1. Exceeding these ratings may permanently damage the M-991.
Absolute Maximum Ratings are stress ratings. Stresses in
excess of these ratings can cause permanent damage to
the device. Functional operation of the device at these or
any other conditions beyond those indicated in the opera-
tional sections of this data sheet is not implied. Exposure of
the device to the absolute maximum ratings for an extend-
ed period may degrade the device and effect its reliability.
Current Drain, IDD
Deviation from (VDD + VSS)/2
Internal Resistance from VREF
to VDD, VSS
External Clock: (XOUT open)
XIN, XOUT Loading:
OUTDRIVE Envelope Rise Time
DX, CE Pns:
VOL (ISINK = -100 µA)
VOH (ISOURCE = 100 µA)
Data Setup (tDS)
Data Hold (tDH)
Chip Enable Fall (tPL)
Tone On Delay (tTO)
Tone Off Delay (tTD)
Mute Delay from Outdrive (tMO)
Notes: (unless otherwise specified)
All DC voltages are
Vrms per tone, 540
3. Any one frequency relative to the lowest level output tone (f<4000 Hz).
4. 0 dBm = 0.775 Vrms.
5. To 90% maximum amplitude.
6. For all supply voltages in the operating range.
VDD - 0.2
VDD - 1.5
- +2 %
- 6.75 kΩ
- +0.01 %
- 0.2 V
- VDD V
- 60 %
- 10 pF
- - MΩ
- +0.5 %
- 180 mV
- - dB
- -60 dBm
- 4 ms
- 0.5 V
7. At XOUT pin as compared to 3.579545 MHz.
8. OUTDRIVE with load >5 KW/OUTDRIVE with
540 W load.
9. Resistance at VREF to VDD or VSS > 1 MW.
10. Crystal oscillator active.
11. Measured 90% to 10%.
Call Progress Tone Generation
Call progress tones are audible tones sent from
switching systems to calling parties (or equipment) to
indicate the status of calls. Calling parties can identify
the success of a placed call by what is heard after dial-
ing. The M-991 series utilizes a highly linear tone gen-
erator that produces the unique frequencies (singly or
in pairs) that are common to call progress signals.
Duration and frequency selection are digitally con-
trolled (see the Data/Tone Selection table below for
data settings for a particular tone output). A typical
control sequence for the M-991 is: (1) set data lines to
desired frequency selection, (2) wait for data lines to
settle, (3) drive the chip enable (CE) low, (4) maintain
CE low for desired tone duration (Note: data lines may
be changed after data hold time), and (4) return CE to
a logic high. (Commonly used call progress tones are
shown in the Data/Tone Selection table below.) In a
bus-oriented system, noise on the data lines may
propagate through the device and appear at the out-
put. To safeguard against this, use an external latch to
lock the data into the device. In addition, it is good
practice to bypass the VREF pin to ground with a small
capacitor (0.01 mF) to reduce power supply noise. The
designer should be aware of device timing require-
ments and design accordingly. The data input pins
may be tied high (+5 VDC) or low (ground) as required,
but D4 and D5 must be left open. Beware of hardwiring
the CE pin for dedicated tone generation. This input is
edge triggered. An RC network like that shown in the
Power-on Reset Circuit on Page 4 should be used to
momentarily reset the device immediately following
power-up to ensure proper operation.
D0 D1 D2 D3 Frequency (Hz)
0 0 0 0 350
440 Dial Tone
0 0 0 1 400
0 0 1 0 440
off Alert Tone
0 0 1 1 440
480 Audible Ring
0 1 0 0 440
0 1 0 1 480
off Bell high tone
0 1 1 0 480
620 Reorder(Bell low)
0 1 1 1 350
1 0 0 0 620
1 0 0 1 941
1209 DTMF “*”
Standard Call Progress Tones
D0 - D3
Latches data and enables output (active
Data input pins. (See Data/Tone Selection.)
Output indicates that a signal is being generated at
Linear buffered tone output.
Most positive power supply input pin.
Internally generated mid-power supply voltage
Most negative power supply input pin.
Crystal oscillator or digital clock input.
Crystal oscillator output.
Repeat, tones on and off 250 ms ± 25 ms each.
Repeat, tones on and off 500 ms ± 50 ms each.
Reat, tones on 2 ± 0.2 s, tones off 4 ± 0.4 s
Three bursts tones on and off 100 ms ± 20 ms each followed by dial tone.
Tones on 1 ± 0.2s, followed by single 440 Hz on for 0.2s on, and silence for 3 ±
0.3 s, repeat.
Repeat alternating tones, each on for 230 ms ± 70 ms with total cycle of 500 ±
One burst 200 ± 100 ms
One burst of tone on 1.75 ± 0.25 s before attendant intrudes, followed by burst
of tone 0.65 ± 0.15 s on, 8 to 20 s apart for as long as the call lasts
One burst of tone for 3 ± 1 s before overriding station intrudes
Three bursts on and off 100 ms each or 100 ms on, 100 ms off, 300 ms on
Rev. 1 www.clare.com
Power-on Reset Circuit
Expanded Timing Diagram
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