DatasheetBay.com



M-984-02S (Clare Inc.) : Total 6 Pages

No Preview Available !

[ Download PDF for PC ]

Features
Detects single-frequency tones used for error
indication and call progress in telephone systems
Provides detection windows for:
400/425 Hz (Call Progress)
950 Hz (Special and error indication)
1400 Hz (Special and error indication)
1800 Hz (Special and error indication)
Separate tri-state outputs for each tone window
Inexpensive 3.58 MHz crystal time base
Auxiliary 3.58 MHz clock output
14-pin DIP package and 16-pin SOIC package
Single supply 3 to 5 volt (low power CMOS)
Wide dynamic range (30 dBm)
Applications
Automatic dialers
Modems
Telecom test equipment
Telephone traffic measurement,
Service evaluation
Billing equipment
Pin Diagram
M-984-02
Special Information Tone Detector
Description
The M-984-02 Special Information Tone Detector is a
monolithic integrated circuit designed to provide reli-
able detection of many common telephone network
status signals. In particular, it detects the signals
known as Special Information Tones (SITs) or error
tones as defined by the CCITT, and single tones often
used as dial tone, audible ringing, and other general
progress indications. The M-984-02 uses CMOS
switched capacitor filters and a crystal time base to
achieve the high stability and accuracy specified. Each
tone detection window has an associated output pin,
which can be placed in a high impedance state for use
with time-share microcomputer bus applications.
In comparison with the earlier M-984, the M-984-02
has wider acceptance bands for SIT tones to facilitate
reception of tape-loop tones, lower power consump-
tion at 5V operation, 3V operation, superior tempera-
ture performance, lower cost, and is available in DIP,
SOIC, and SOIC tape and reel versions.
Ordering Information
Part #
M-984-02P
M-984-02S
M-984-02T
Description
14-pin plastic DIP
16-pin plastic, SOIC
16-pin SOIC, Tape and Reel
Block Diagram
DS-M984-02-R3
www.clare.com
1



No Preview Available !

[ Download PDF for PC ]

M-984-02
Absolute Maximum Ratings
DC Supply Voltage
7V
Input Voltage on SIGIN
Input Voltage on Any Pin
(except SIGIN)
VSS - 6.5V to VDD +0.3V
VSS - 0.3 to VDD + 0.3V
Storage Temperature Range
-40°C to +150°C
Operating Temperature Range
-40°C to +85°C
Lead Soldering Temperature
260°C for 5 seconds
Note:
Exceeding these ratings may permanently damage the device.
Absolute Maximum Ratings are stress ratings. Stresses in
excess of these ratings can cause permanent damage to
the device. Functional operation of the device at these or
any other conditions beyond those indicated in the opera-
tional sections of this data sheet is not implied. Exposure of
the device to the absolute maximum ratings for an extend-
ed period may degrade the device and effect its reliability.
Specifications
Parameter
Conditions
Operating Conditions
VDD
Power supply noise
-
0.1 - 5 kHz
Power
VREF
Current drain (IDD)
VREF
Impedance
VREF open
-
-
Signal Detection
Frequency Range
-
Level: VDD = 5.0V
Level: VDD = 3.0V
Duration
Bridge Time
-
-
fc = 400 Hz
fc = 950, 1400, 1800 Hz
-
Signal to Noise Ratio
-
Signal Rejection
Frequency Range
-
Level: VDD = 5.0V
Level: VDD = 3.0V
Duration
-
-
-
Outputs
Inputs
Except X358
Dn pins only
EN pin
VOL
VOH
IOZ
VIL
VIH
Pull-up and Pull-
down currents
MODE = VSS
/XRANGE +VSS
MODE2 = VDD
SIGIN pin
PD = VDD
Voltage range
ISINK = -1.0 mA
ISOURCE = 1.0 mA
VO = VDD, VSS
-
VDD = 5V
VDD = 2.7V
VDD = 5V
VDD = 2.7V
-
VDD = 5V
VDD = 2.7V
-
-
Input impedance
f = 500 Hz
Input Spectrum
-
Clock
External clock
connected to
XIN pin
VIL
VIH
Duty cycle
XOUT open
XOUT open
XOUT open
XIN, XOUT with Capacitance
crystal ocs. active Internal res.
-
-
Tri-state Operation
X358 pin
VOL
VOH
Duty cycle
tEN (High Z to Low Z)
tDE (Low Z to High Z)
CL = 20 pF, ISINK = -1.0 mA
CL = 20 pF, ISOURCE = 1.0 mA
CL = 20 pF
CL = 50 pF
RL = 100 K
Unless otherwise noted, specifications hold over VDD - VSS = 2.8V to 5.5V power supply, and TOL -40°C to +85°C.
Notes:
1. See the Detector Frequency Windows table on page 4 for detection/ rejection frequencies.
2 www.clare.com
Min
2.7
-
-
48% of VDD
3.25
Note 1
-30 (24.5 mV)
-33 (17.4 mV)
85
50
-
16
Note 1
-
-
-
-
VDD-0.5
-
-
VDD -2.0
VDD - 0.5
12.5
4
2
12.5
12.5
4
-6.5
80
-
-
VDD - 0.2
40
-
20
-
VDD - 0.5
40
-
-
Max
5.5
20
15
52% of VDD
8.25
Note 1
0 (775 mV)
-3 (173.5 mV)
-
-
15
-
Note 1
-40 (7.8 mV)
-43 (5.5 mV)
50
0.5
-
1
0.5
-
-
50
20
6
100
25
10
VDD
-
28
0.2
-
60
10
-
0.5
-
60
250
250
Units
V
mV p-p
mA
V
k
-
dBm
dBm
ms
ms
ms
dB
-
dBm
dBm
ms
V
V
µA
V
V
V
µA
µA
µA
µA
µA
µA
V
k
kHz
V
V
%
pF
M
V
V
%
ns
ns
Rev. 3



No Preview Available !

[ Download PDF for PC ]

M-984-02
Pin Functions
PIN FUNCTION
XIN
XOUT
Crystal Connection — 3.58 MHz crystal across these pins will produce the timebase needed for proper operation of the
M-984-02. An external clock signal may be fed to XIN providing the clock signal has a duty cycle of 50 ±10% and comes within
0.2 volts of the supply rails. XOUT remains unconnected when an external clock is used.
X358 A buffered output pin. A 3.58 MHz clock signal is available for use in other circuits as a timebase. Leave open when unused.
ENVLP
VSS
VDD
SIGIN
The ENVLP pin is a common detection indicator for the four detect pins. Simply put, the ENVLP is a logical “OR” of the active
detect circuits for each of the four windows, though there is a delay provided to permit ENVLP to latch the first active detect pin.
ENVLP is not tri-state controlled.
The power supply pins, VDD being the most positive. Commonly, VDD is at 3-5 volts, white VSS is at ground.
Analog signal input. (Internally capacitively coupled.)
VREF VREF is a bias voltage generated in the chip for use in external analog circuits, such as active filters and AC-coupled buffers.
Leave open when unused.
OE The tri-state control pin. OE places the DET pins in the active mode when at logic “1”. When at logic “0,” OE causes the DET
outputs to appear as high impedance. Should be tied to logic “1” when the M-984-02 is not used in a time-shared bus
application.
D1800
D1400
D950
D400
The detect outputs associated with each window. Tri-state control is available through use of the OE pin.
Timing is shown in the Timing Diagram on page 4.
Rev. 3
www.clare.com
3



No Preview Available !

[ Download PDF for PC ]

M-984-02
Typical Application
Detector Frequency Windows
Detector
D400
D950
D1400
D1800
Low Reject
363
835
1275
1656
Timing Diagram
Low Accept
392
885
1328
1722
High Accept
459
1016
1472
1854
High Reject
493
1070
1527
1924
Tri-State Timing
4
www.clare.com
Rev. 3






[ Download PDF for PC ]






0  1  2  3  4  5  6  7  8  9  A  B  C  D  E  F  G  H  I  J  K  L  M  N  O  P  Q  R  S  T  U  V  W  X  Y  Z  

This is a individually operated, non profit site. If this site is good enough to show, please introduce this site to others.
* 2015 :: DatasheetBay.com :: DatasheetBay